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Searched refs:tcg_target_available_regs (Results 1 – 11 of 11) sorted by relevance

/qemu/tcg/riscv/
H A Dtcg-target.c.inc3046 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
3047 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
3075 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
3076 tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS;
3077 tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS;
3081 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
3082 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
3083 tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS;
3089 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
3090 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
[all …]
/qemu/tcg/
H A Dtcg.c261 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; variable
3784 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); in la_reset_pref()
3903 set = tcg_target_available_regs[ts->type] & mask; in la_cross_call()
4101 tcg_target_available_regs[ts->type]; in liveness_pass_1()
4330 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; in liveness_pass_1()
4714 temp_load(s, ts, tcg_target_available_regs[ts->type], in temp_sync()
5069 temp_load(s, ts, tcg_target_available_regs[itype], in tcg_reg_alloc_mov()
5103 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], in tcg_reg_alloc_mov()
5371 temp_load(s, ts, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
5467 nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc2679 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2680 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2695 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2696 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2698 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
/qemu/tcg/tci/
H A Dtcg-target.c.inc1273 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
1275 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc3391 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
3392 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
3393 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3394 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/s390x/
H A Dtcg-target.c.inc3731 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
3732 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
3734 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3735 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/i386/
H A Dtcg-target.c.inc4769 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
4771 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
4774 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
4775 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
4778 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc2115 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2116 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
/qemu/tcg/ppc/
H A Dtcg-target.c.inc4504 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
4505 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4507 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
4508 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/qemu/tcg/arm/
H A Dtcg-target.c.inc2724 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2735 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2736 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
/qemu/tcg/mips/
H A Dtcg-target.c.inc2751 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2753 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;