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Searched refs:tcg_regset_set_reg (Results 1 – 12 of 12) sorted by relevance

/qemu/tcg/sparc64/
H A Dtcg-target.c.inc996 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1002 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
2119 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
2120 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2);
2121 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3);
2122 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4);
2123 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5);
2124 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6);
2125 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7);
2126 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0);
[all …]
/qemu/tcg/mips/
H A Dtcg-target.c.inc2593 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2757 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2758 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2759 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2760 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2761 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2762 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2763 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2764 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2765 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
[all …]
/qemu/tcg/s390x/
H A Dtcg-target.c.inc3739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
3740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
3741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
3742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
3743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
3744 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
3747 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
3749 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
3751 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
3752 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
[all …]
/qemu/tcg/ppc/
H A Dtcg-target.c.inc2827 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
4512 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
4513 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
4514 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
4515 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
4516 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
4517 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
4518 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
4519 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
4520 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
[all …]
/qemu/tcg/arm/
H A Dtcg-target.c.inc2727 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
[all …]
/qemu/tcg/i386/
H A Dtcg-target.c.inc4717 tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
4782 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
4783 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
4784 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
4787 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI);
4788 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI);
4790 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
4791 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
4792 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
4793 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc2634 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2711 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2712 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
2713 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
2714 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
2715 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2716 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
2717 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
2718 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
/qemu/tcg/
H A Dtcg.c2031 tcg_regset_set_reg(s->reserved_regs, reg); in tcg_global_reg_new_internal()
4122 tcg_regset_set_reg(*la_temp_pref(ts), in liveness_pass_1()
5176 tcg_regset_set_reg(allocated_regs, its->reg); in tcg_reg_alloc_dup()
5436 tcg_regset_set_reg(i_allocated_regs, reg - 1); in tcg_reg_alloc_op()
5442 tcg_regset_set_reg(i_allocated_regs, reg); in tcg_reg_alloc_op()
5459 tcg_regset_set_reg(t_allocated_regs, reg); in tcg_reg_alloc_op()
5460 tcg_regset_set_reg(t_allocated_regs, reg + 1); in tcg_reg_alloc_op()
5504 tcg_regset_set_reg(i_allocated_regs, reg); in tcg_reg_alloc_op()
5589 tcg_regset_set_reg(o_allocated_regs, reg); in tcg_reg_alloc_op()
5978 tcg_regset_set_reg(allocated_regs, itsl->reg); in tcg_reg_alloc_dup2()
[all …]
/qemu/tcg/riscv/
H A Dtcg-target.c.inc2959 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
3064 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
3065 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
3066 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
3067 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
3068 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
3069 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
3070 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
3094 tcg_regset_set_reg(s->reserved_regs, TCG_REG_V0);
/qemu/include/tcg/
H A Dtcg.h75 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) macro
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc3418 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
3419 tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
3420 tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
3421 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
3422 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
3423 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
3424 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
3478 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
/qemu/tcg/tci/
H A Dtcg-target.c.inc1286 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
1287 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);