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Searched refs:tcg_global_mem_new_i32 (Results 1 – 17 of 17) sorted by relevance

/qemu/target/sh4/
H A Dtranslate.c99 cpu_gregs[i] = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
105 cpu_pc = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
107 cpu_sr = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
109 cpu_sr_m = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
111 cpu_sr_q = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
113 cpu_sr_t = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
115 cpu_ssr = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
117 cpu_spc = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
119 cpu_gbr = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
121 cpu_vbr = tcg_global_mem_new_i32(tcg_env, in sh4_translate_init()
[all …]
/qemu/target/avr/
H A Dtranslate.c130 cpu_pc = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(pc_w), "pc"); in avr_cpu_tcg_init()
131 cpu_Cf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregC), "Cf"); in avr_cpu_tcg_init()
132 cpu_Zf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregZ), "Zf"); in avr_cpu_tcg_init()
133 cpu_Nf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregN), "Nf"); in avr_cpu_tcg_init()
134 cpu_Vf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregV), "Vf"); in avr_cpu_tcg_init()
135 cpu_Sf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregS), "Sf"); in avr_cpu_tcg_init()
136 cpu_Hf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregH), "Hf"); in avr_cpu_tcg_init()
137 cpu_Tf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregT), "Tf"); in avr_cpu_tcg_init()
138 cpu_If = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregI), "If"); in avr_cpu_tcg_init()
139 cpu_rampD = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampD), "rampD"); in avr_cpu_tcg_init()
[all …]
/qemu/target/xtensa/
H A Dtranslate.c156 cpu_pc = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
160 cpu_R[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
166 cpu_FR[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
180 cpu_MR[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
187 cpu_BR[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
192 cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
198 cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
207 cpu_SR[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
216 cpu_UR[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
224 tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
[all …]
/qemu/include/tcg/
H A Dtcg-op.h66 #define tcg_global_mem_new tcg_global_mem_new_i32
H A Dtcg-op-common.h28 TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *name);
/qemu/target/openrisc/
H A Dtranslate.c100 cpu_dflag = tcg_global_mem_new_i32(tcg_env, in openrisc_translate_init()
121 fpcsr = tcg_global_mem_new_i32(tcg_env, in openrisc_translate_init()
/qemu/target/rx/
H A Dtranslate.c2269 cpu_##sym = tcg_global_mem_new_i32(tcg_env, \
2281 cpu_regs[i] = tcg_global_mem_new_i32(tcg_env, in rx_translate_init()
/qemu/target/arm/tcg/
H A Dtranslate.c66 cpu_R[i] = tcg_global_mem_new_i32(tcg_env, in arm_translate_init()
70 cpu_CF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, CF), "CF"); in arm_translate_init()
71 cpu_NF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, NF), "NF"); in arm_translate_init()
72 cpu_VF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, VF), "VF"); in arm_translate_init()
73 cpu_ZF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, ZF), "ZF"); in arm_translate_init()
/qemu/target/m68k/
H A Dtranslate.c72 QREG_##name = tcg_global_mem_new_i32(tcg_env, \ in m68k_tcg_init()
81 cpu_halted = tcg_global_mem_new_i32(tcg_env, in m68k_tcg_init()
84 cpu_exception_index = tcg_global_mem_new_i32(tcg_env, in m68k_tcg_init()
/qemu/target/microblaze/
H A Dtranslate.c1885 tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name); in mb_tcg_init()
/qemu/target/ppc/
H A Dtranslate.c95 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, in ppc_translate_init()
163 cpu_access_type = tcg_global_mem_new_i32(tcg_env, in ppc_translate_init()
/qemu/target/i386/tcg/
H A Dtranslate.c3711 cpu_cc_op = tcg_global_mem_new_i32(tcg_env, in tcg_x86_init()
/qemu/target/mips/tcg/
H A Dtranslate.c15287 hflags = tcg_global_mem_new_i32(tcg_env, in mips_tcg_init()
15290 fpu_fcr0 = tcg_global_mem_new_i32(tcg_env, in mips_tcg_init()
15293 fpu_fcr31 = tcg_global_mem_new_i32(tcg_env, in mips_tcg_init()
/qemu/target/hppa/
H A Dtranslate.c322 cpu_psw_xb = tcg_global_mem_new_i32(tcg_env, in hppa_translate_init()
/qemu/target/sparc/
H A Dtranslate.c5893 *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name); in sparc_tcg_init()
/qemu/target/s390x/tcg/
H A Dtranslate.c209 cc_op = tcg_global_mem_new_i32(tcg_env, offsetof(CPUS390XState, cc_op), in s390x_translate_init()
/qemu/tcg/
H A Dtcg.c2104 TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *name) in tcg_global_mem_new_i32() function