| /qemu/target/mips/tcg/ |
| H A D | msa_translate.c | 215 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_check_zero_element()
233 tcg_gen_setcondi_i64(cond, t0, t0, 0); in gen_msa_BxZ_V()
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| H A D | translate.c | 3838 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max); in gen_loongson_multimedia()
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| /qemu/include/tcg/ |
| H A D | tcg-op.h | 212 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
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| H A D | tcg-op-common.h | 232 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
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| /qemu/target/ppc/ |
| H A D | translate.c | 1829 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_divd()
1830 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divd()
1832 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divd()
1838 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divd()
1898 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); in gen_op_arith_modd()
1899 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modd()
1901 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_modd()
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| /qemu/target/tricore/ |
| H A D | translate.c | 506 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_madd32_d()
508 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1007 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_madd32_q()
1008 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1216 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); in gen_msub32_d()
1218 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1740 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msub32_q()
1747 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); in gen_msub32_q()
1748 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
1914 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); in gen_msubs32_q()
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| /qemu/target/ppc/translate/ |
| H A D | vmx-impl.c.inc | 1153 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1156 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
3372 tcg_gen_setcondi_i64(TCG_COND_EQ, t0, a, INT64_MIN); \
3373 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, -1); \
3375 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, 0); \
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| H A D | fixedpoint-impl.c.inc | 1164 tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
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| /qemu/target/openrisc/ |
| H A D | translate.c | 330 tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); in gen_muldu()
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| /qemu/tcg/ |
| H A D | tcg-op.c | 1938 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, in tcg_gen_setcondi_i64() function
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| /qemu/target/loongarch/tcg/insn_trans/ |
| H A D | trans_vec.c.inc | 4763 tcg_gen_setcondi_i64(COND, t1, t1, 0); \
4809 tcg_gen_setcondi_i64(COND, t1, t1, 0); \
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| /qemu/target/sparc/ |
| H A D | translate.c | 2394 tcg_gen_setcondi_i64(cmp->cond, c64, cmp->c1, cmp->c2); in gen_fmovs()
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| /qemu/target/s390x/tcg/ |
| H A D | translate.c | 580 tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0); in gen_op_calc_cc()
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| /qemu/target/i386/tcg/ |
| H A D | emit.c.inc | 1833 tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0);
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| /qemu/target/arm/tcg/ |
| H A D | translate-a64.c | 3014 tcg_gen_setcondi_i64(TCG_COND_NE, tmp, tmp, 0); in gen_store_exclusive()
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