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Searched refs:tcg_gen_ori_i32 (Results 1 – 17 of 17) sorted by relevance

/qemu/target/ppc/translate/
H A Dstorage-ctrl-impl.c.inc146 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
247 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
H A Dspe-impl.c.inc284 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
/qemu/target/microblaze/
H A Dtranslate.c503 DO_TYPEBI(ori, false, tcg_gen_ori_i32) in DO_TYPEA_CFG()
1175 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); in DO_BCC()
1222 tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); in trans_brki()
1355 tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); in do_msrclrset()
1528 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); in do_rti()
1549 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); in do_rte()
/qemu/include/tcg/
H A Dtcg-op.h320 #define tcg_gen_ori_tl tcg_gen_ori_i32
H A Dtcg-op-common.h88 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
/qemu/target/sh4/
H A Dtranslate.c463 tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); in _decode_opc()
1248 tcg_gen_ori_i32(REG(0), REG(0), B7_0); in _decode_opc()
1257 tcg_gen_ori_i32(val, val, B7_0); in _decode_opc()
/qemu/target/arm/tcg/
H A Dtranslate.h374 tcg_gen_ori_i32(p, p, bits); in set_pstate_bits()
H A Dtranslate-vfp.c163 tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); in gen_update_fp_context()
203 tcg_gen_ori_i32(control, control, bits); in gen_update_fp_context()
H A Dtranslate.c1391 tcg_gen_ori_i32(tmp, tmp, 2); in IWMMXT_OP()
1399 tcg_gen_ori_i32(tmp, tmp, 1); in gen_op_iwmmxt_set_cup()
3960 tcg_gen_ori_i32(tmp, tmp, a->imm << 16); in trans_MOVT()
/qemu/tcg/
H A Dtcg-op.c424 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) in tcg_gen_ori_i32() function
1766 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); in tcg_gen_ori_i64()
1767 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); in tcg_gen_ori_i64()
H A Dtcg-op-gvec.c3244 tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); in do_gvec_shifts()
/qemu/target/xtensa/
H A Dtranslate.c2083 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); in translate_rsil()
2159 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm); in translate_setb_expstate()
6290 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); in translate_compare_d()
6318 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); in translate_compare_s()
/qemu/target/m68k/
H A Dtranslate.c2135 tcg_gen_ori_i32(tmp, src1, mask); in DISAS_INSN()
5701 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); in DISAS_INSN()
/qemu/target/ppc/
H A Dtranslate.c5217 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); in gen_tlbsx_40x()
5290 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); in gen_tlbsx_440()
/qemu/target/i386/tcg/
H A Dtranslate.c730 tcg_gen_ori_i32(t, t, mask); in gen_set_hflag()
/qemu/target/hppa/
H A Dtranslate.c4176 tcg_gen_ori_i32(dst, src, INT32_MIN); in gen_fnegabs_f()
/qemu/target/sparc/
H A Dtranslate.c220 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit); in gen_update_fprs_dirty()