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Searched refs:tcg_gen_movcond_i32 (Results 1 – 21 of 21) sorted by relevance

/qemu/tcg/
H A Dtcg-op.c764 tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); in tcg_gen_ctz_i32()
1072 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, in tcg_gen_movcond_i32() function
1352 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); in tcg_gen_smin_i32()
1357 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i32()
1362 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); in tcg_gen_smax_i32()
1367 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i32()
2830 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero, in tcg_gen_movcond_i64()
2832 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero, in tcg_gen_movcond_i64()
H A Dtcg-op-ldst.c838 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); in tcg_gen_nonatomic_cmpxchg_i32_int()
H A Dtcg-op-gvec.c2269 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i32()
2311 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i32()
/qemu/target/arm/tcg/
H A Dtranslate-vfp.c390 tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm); in trans_VSEL()
393 tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, frn, frm); in trans_VSEL()
398 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm); in trans_VSEL()
401 tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, frn, frm); in trans_VSEL()
404 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm); in trans_VSEL()
H A Dgengvec.c1030 tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i32()
1031 tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i32()
1148 tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero); in gen_sshl_i32()
1149 tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval); in gen_sshl_i32()
1650 tcg_gen_movcond_i32(TCG_COND_LT, d, a, b, d, t); in gen_sabd_i32()
1707 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i32()
H A Dtranslate-m-nocp.c541 tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), in gen_M_fp_sysreg_read()
H A Dtranslate.c538 tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \
6102 tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf); in op_smlad()
6942 tcg_gen_movcond_i32(TCG_COND_LEU, masklen, in trans_VCTP()
7296 tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm); in trans_CSEL()
H A Dtranslate-a64.c844 tcg_gen_movcond_i32(TCG_COND_GTU, d, in gen_vfp_ah_negh()
855 tcg_gen_movcond_i32(TCG_COND_GTU, d, in gen_vfp_ah_negs()
883 tcg_gen_movcond_i32(TCG_COND_GTU, d, in gen_vfp_ah_absh()
893 tcg_gen_movcond_i32(TCG_COND_GTU, d, in gen_vfp_ah_abss()
H A Dtranslate-sve.c2443 tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); in incr_last_active()
2457 tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); in wrap_last_active()
/qemu/include/tcg/
H A Dtcg-op.h383 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
H A Dtcg-op-common.h133 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
/qemu/target/m68k/
H A Dtranslate.c3426 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in shift_reg()
3432 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, in shift_reg()
3472 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, in shift_reg()
3637 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); in rotate_x()
3716 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); in rotate32_x()
3717 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); in rotate32_x()
3810 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN()
3841 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN()
3873 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN()
/qemu/target/sh4/
H A Dtranslate.c772 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2); in _decode_opc()
889 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc()
911 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc()
/qemu/target/xtensa/
H A Dtranslate.c1836 tcg_gen_movcond_i32(par[0], arg[0].out, in translate_movcond()
1853 tcg_gen_movcond_i32(par[0], in translate_movp()
2218 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, in translate_s32ex()
6294 tcg_gen_movcond_i32(TCG_COND_NE, in translate_compare_d()
6323 tcg_gen_movcond_i32(TCG_COND_NE, in translate_compare_s()
6506 tcg_gen_movcond_i32(par[0], arg[0].out, in translate_movcond_s()
6536 tcg_gen_movcond_i32(par[0], in translate_movp_s()
/qemu/target/rx/
H A Dtranslate.c733 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, in stcond()
1816 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
/qemu/target/ppc/
H A Dtranslate.c1793 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw()
1799 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw()
1874 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_modw()
1880 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); in gen_op_arith_modw()
4356 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); in gen_setb()
/qemu/target/sparc/
H A Dtranslate.c804 tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); in gen_op_fpadds32s()
822 tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); in gen_op_fpsubs32s()
2402 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); in gen_fmovs()
/qemu/target/microblaze/
H A Dtranslate.c1138 tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, in DO_BR()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc3339 tcg_gen_movcond_i32(TCG_COND_EQ, b, b, zero, one, b); \
3354 tcg_gen_movcond_i32(TCG_COND_NE, b, t0, t1, t0, b); \
/qemu/target/mips/tcg/
H A Dtranslate.c9217 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); in gen_sel_s()
9221 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); in gen_sel_s()
9225 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); in gen_sel_s()
/qemu/target/i386/tcg/
H A Demit.c.inc3817 tcg_gen_movcond_i32(TCG_COND_EQ, decode->cc_op_dynamic, count32, tcg_constant_i32(0),