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Searched refs:tcg_gen_andi_i32 (Results 1 – 25 of 32) sorted by relevance

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/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c135 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); in trans_VSCCLRM()
137 tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); in trans_VSCCLRM()
298 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); in gen_branch_fpInactive()
300 tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); in gen_branch_fpInactive()
335 tcg_gen_andi_i32(qc, tmp, FPSR_QC); in gen_M_fp_sysreg_write()
343 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
345 tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
393 tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
460 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCVQC_MASK); in gen_M_fp_sysreg_read()
469 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in gen_M_fp_sysreg_read()
[all …]
H A Dtranslate.c314 tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); in store_reg()
319 tcg_gen_andi_i32(var, var, ~3); in store_reg()
451 tcg_gen_andi_i32(tmp, tmp, 0x8000); in gen_add16()
452 tcg_gen_andi_i32(t0, t0, ~0x8000); in gen_add16()
453 tcg_gen_andi_i32(t1, t1, ~0x8000); in gen_add16()
535 tcg_gen_andi_i32(tmp1, t1, 0x1f); \
537 tcg_gen_andi_i32(tmp1, t1, 0xe0); \
548 tcg_gen_andi_i32(tmp1, t1, 0xff); in GEN_SHIFT()
628 case 3: tcg_gen_andi_i32(shift, shift, 0x1f); in gen_arm_shift_reg()
750 tcg_gen_andi_i32(cpu_R[15], var, ~1); in gen_bx()
[all …]
H A Dtranslate.h386 tcg_gen_andi_i32(p, p, ~bits); in clear_pstate_bits()
416 tcg_gen_andi_i32(d, s, INT16_MAX); in gen_vfp_absh()
421 tcg_gen_andi_i32(d, s, INT32_MAX); in gen_vfp_abss()
H A Dtranslate-neon.c1992 tcg_gen_andi_i32(var, var, 0xffff0000); in gen_neon_dup_high16()
3258 tcg_gen_andi_i32(rd, rd, 0xff00ff00); in gen_neon_trn_u8()
3259 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); in gen_neon_trn_u8()
3263 tcg_gen_andi_i32(t1, t1, 0x00ff00ff); in gen_neon_trn_u8()
3264 tcg_gen_andi_i32(tmp, t0, 0xff00ff00); in gen_neon_trn_u8()
3277 tcg_gen_andi_i32(tmp, t1, 0xffff); in gen_neon_trn_u16()
3280 tcg_gen_andi_i32(tmp, t0, 0xffff0000); in gen_neon_trn_u16()
H A Dtranslate-vfp.c165 tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); in gen_update_fp_context()
409 tcg_gen_andi_i32(dest, dest, 0xffff); in trans_VSEL()
837 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in trans_VMSR_VMRS()
873 tcg_gen_andi_i32(tmp, tmp, 1 << 30); in trans_VMSR_VMRS()
916 tcg_gen_andi_i32(tmp, tmp, 0xffff); in trans_VMOV_half()
H A Dgengvec.c1961 tcg_gen_andi_i32(t, t, 1); in gen_shadd_i32()
2033 tcg_gen_andi_i32(t, t, 1); in gen_uhadd_i32()
2105 tcg_gen_andi_i32(t, t, 1); in gen_shsub_i32()
2177 tcg_gen_andi_i32(t, t, 1); in gen_uhsub_i32()
2249 tcg_gen_andi_i32(t, t, 1); in gen_srhadd_i32()
2321 tcg_gen_andi_i32(t, t, 1); in gen_urhadd_i32()
H A Dtranslate-a64.c346 tcg_gen_andi_i32(tmp, tmp, 15); in check_lse2_align()
2391 tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); in gen_get_nzcv()
2412 tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); in gen_set_nzcv()
2414 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); in gen_set_nzcv()
2417 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); in gen_set_nzcv()
2420 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); in gen_set_nzcv()
8531 tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); in TRANS()
/qemu/target/sh4/
H A Dtranslate.c201 tcg_gen_andi_i32(cpu_sr, src, in gen_write_sr()
444 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S)); in _decode_opc()
743 tcg_gen_andi_i32(cmp1, cmp1, 0x80808080); in _decode_opc()
776 tcg_gen_andi_i32(t1, t1, 1); in _decode_opc()
861 tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); in _decode_opc()
876 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
898 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
925 tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); in _decode_opc()
1134 tcg_gen_andi_i32(REG(0), REG(0), B7_0); in _decode_opc()
1143 tcg_gen_andi_i32(val, val, B7_0); in _decode_opc()
[all …]
/qemu/target/microblaze/
H A Dtranslate.c322 tcg_gen_andi_i32(out, ina, ~imm); in DO_TYPEA()
326 DO_TYPEBI(andi, false, tcg_gen_andi_i32) in DO_TYPEA()
333 tcg_gen_andi_i32(tmp, inb, 31); in DO_TYPEA()
340 tcg_gen_andi_i32(tmp, inb, 31); in gen_bsrl()
347 tcg_gen_andi_i32(tmp, inb, 31); in gen_bsll()
566 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in DO_TYPEA()
575 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in gen_src()
581 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in gen_srl()
1219 tcg_gen_andi_i32(cpu_msr, cpu_msr, in trans_brki()
1357 tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); in do_msrclrset()
[all …]
/qemu/target/m68k/
H A Dtranslate.c1648 tcg_gen_andi_i32(t0, t0, 0x22); in bcd_add()
1703 tcg_gen_andi_i32(t2, t2, 0x22); in bcd_sub()
1714 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); in bcd_flags()
1879 tcg_gen_andi_i32(src2, DREG(insn, 9), 7); in DISAS_INSN()
1881 tcg_gen_andi_i32(src2, DREG(insn, 9), 31); in DISAS_INSN()
2123 tcg_gen_andi_i32(QREG_CC_Z, src1, mask); in DISAS_INSN()
2132 tcg_gen_andi_i32(tmp, src1, ~mask); in DISAS_INSN()
2161 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); in gen_get_sr()
2543 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); in DISAS_INSN()
3080 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); in gen_subx()
[all …]
/qemu/scripts/coccinelle/
H A Dtcg_gen_extract.cocci55 tcg_gen_andi_i32@and_p
96 -tcg_gen_andi_i32@and_p(ret, ret, msk);
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmov.c.inc104 tcg_gen_andi_i32(temp, temp, mask);
105 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
/qemu/target/rx/
H A Dtranslate.c1317 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); in trans_SHLL_rr()
1346 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_imm()
1373 tcg_gen_andi_i32(count, cpu_regs[rs], 31); in shiftr_reg()
1376 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_reg()
1438 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); in trans_RORC()
1459 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in rx_rot()
1514 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); in trans_REVW()
1517 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); in trans_REVW()
1983 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
1994 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
[all …]
/qemu/target/mips/tcg/
H A Dmxu_translate.c2203 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2211 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2234 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2235 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2243 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2244 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2297 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
2307 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); in gen_mxu_Q8MAX_Q8MIN()
2333 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
2334 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
[all …]
H A Dtranslate.c1243 tcg_gen_andi_i32(t2, t2, 0xf); in gen_load_srsgpr()
1263 tcg_gen_andi_i32(t2, t2, 0xf); in gen_store_srsgpr()
2849 tcg_gen_andi_i32(t2, t2, 0x1f); in gen_shift()
8695 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8701 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8706 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8711 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8722 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8732 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
8746 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1()
[all …]
/qemu/target/xtensa/
H A Dtranslate.c292 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); in gen_right_shift_sar()
305 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); in gen_left_shift_sar()
525 tcg_gen_andi_i32(addr, addr, ~0 << memop_alignment_bits(mop)); in gen_load_store_alignment()
1383 tcg_gen_andi_i32(tmp, arg[1].in, 0x1f); in translate_bb()
1398 tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm); in translate_bbi()
1400 tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm); in translate_bbi()
1450 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); in translate_bp()
1500 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm)); in translate_clrb_expstate()
1574 tcg_gen_andi_i32(arg[0].out, tmp, maskimm); in translate_extui()
1852 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); in translate_movp()
[all …]
/qemu/tcg/
H A Dtcg-op-gvec.c1909 tcg_gen_andi_i32(t1, a, ~0xffff); in tcg_gen_vec_add16_i32()
2092 tcg_gen_andi_i32(t1, b, ~0xffff); in tcg_gen_vec_sub16_i32()
2842 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shl8i_i32()
2849 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shl16i_i32()
2907 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shr8i_i32()
2914 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shr16i_i32()
2989 tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ in tcg_gen_vec_sar8i_i32()
2991 tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ in tcg_gen_vec_sar8i_i32()
3003 tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ in tcg_gen_vec_sar16i_i32()
3004 tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ in tcg_gen_vec_sar16i_i32()
[all …]
H A Dtcg-op.c389 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) in tcg_gen_andi_i32() function
921 tcg_gen_andi_i32(t1, arg2, mask); in tcg_gen_deposit_i32()
926 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); in tcg_gen_deposit_i32()
943 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_deposit_z_i32()
963 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_deposit_z_i32()
987 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_extract_i32()
1004 tcg_gen_andi_i32(ret, ret, (1u << len) - 1); in tcg_gen_extract_i32()
1730 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); in tcg_gen_andi_i64()
1731 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); in tcg_gen_andi_i64()
/qemu/target/ppc/translate/
H A Dspe-impl.c.inc166 tcg_gen_andi_i32(t0, arg2, 0x3F);
182 tcg_gen_andi_i32(t0, arg2, 0x3F);
198 tcg_gen_andi_i32(t0, arg2, 0x3F);
210 tcg_gen_andi_i32(t0, arg2, 0x1F);
280 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
368 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
375 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
H A Dfp-impl.c.inc477 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
/qemu/include/tcg/
H A Dtcg-op.h318 #define tcg_gen_andi_tl tcg_gen_andi_i32
H A Dtcg-op-common.h87 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
/qemu/target/ppc/
H A Dtranslate.c2085 tcg_gen_andi_i32(t0, t0, mask); in gen_rlwinm()
2130 tcg_gen_andi_i32(t0, t0, 0x1f); in gen_rlwnm()
2908 tcg_gen_andi_i32(t1, t1, 0x7F); in gen_stswx()
3793 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); in gen_bcond()
3796 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); in gen_bcond()
3872 tcg_gen_andi_i32(t0, t0, bitmask); \
3873 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4190 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); in gen_mtcrf()
4198 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); in gen_mtcrf()
/qemu/target/sparc/
H A Dtranslate.c918 tcg_gen_andi_i32(t0, t0, ~0xff); in gen_op_fmuld8sux16()
923 tcg_gen_andi_i32(t1, t1, ~0xff); in gen_op_fmuld8sux16()
1242 tcg_gen_andi_i32(c1, fcc, 1); in gen_fcompare()
1318 tcg_gen_andi_i32(dst, src, ~(1u << 31)); in gen_op_fabss()
2452 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); in gen_load_trap_state_at_tl()
2779 tcg_gen_andi_i32(trap, trap, mask); in do_tcc()
3026 tcg_gen_andi_i32(tl, tl, MAXTL_MASK); in do_rdhtstate()
3629 tcg_gen_andi_i32(tl, tl, MAXTL_MASK); in TRANS()
/qemu/target/i386/tcg/
H A Dtranslate.c741 tcg_gen_andi_i32(t, t, ~mask); in gen_reset_hflag()
1329 tcg_gen_andi_i32(port, port, 0xffff); in gen_ins()
1345 tcg_gen_andi_i32(port, port, 0xffff); in gen_outs()

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