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Searched refs:tcg_gen_add2_i32 (Results 1 – 12 of 12) sorted by relevance

/qemu/include/tcg/
H A Dtcg-op.h384 #define tcg_gen_add2_tl tcg_gen_add2_i32
H A Dtcg-op-common.h135 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
/qemu/target/sh4/
H A Dtranslate.c773 tcg_gen_add2_i32(REG(B11_8), t1, REG(B11_8), zero, t2, t1); in _decode_opc()
857 tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, in _decode_opc()
922 tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); in _decode_opc()
/qemu/target/rx/
H A Dtranslate.c970 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); in rx_adc()
971 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); in rx_adc()
1008 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); in rx_add()
/qemu/target/arm/tcg/
H A Dtranslate.c485 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, t1, tmp); in gen_add_CC()
4266 tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); in op_mlal()
4311 tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); in trans_UMAAL()
4313 tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); in trans_UMAAL()
4394 tcg_gen_add2_i32(tl, th, tl, th, t0, t1); in DO_QADDSUB()
H A Dtranslate-a64.c989 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); in gen_add32_CC()
/qemu/tcg/
H A Dtcg-op.c1084 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, in tcg_gen_add2_i32() function
1585 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), in tcg_gen_add_i64()
1692 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), in tcg_gen_addi_i64()
/qemu/target/m68k/
H A Dtranslate.c2539 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); in DISAS_INSN()
3077 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, zero, QREG_CC_X, zero); in gen_subx()
3282 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, zero, dest, zero); in gen_addx()
3283 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, zero); in gen_addx()
/qemu/target/microblaze/
H A Dtranslate.c294 tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); in gen_add()
/qemu/target/s390x/tcg/
H A Dtranslate_vx.c.inc1547 tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
/qemu/target/xtensa/
H A Dtranslate.c1778 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16()
/qemu/target/tricore/
H A Dtranslate.c1324 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); in gen_add_CC()