Searched refs:target_arch (Results 1 – 24 of 24) sorted by relevance
54 def kvm_available(target_arch: Optional[str] = None,68 if target_arch:70 if target_arch != host_arch:71 if target_arch != ADDITIONAL_ARCHES.get(host_arch):
1423 target_arch=${1%%-*}1424 case $target_arch in1453 case $target_arch in1469 container_cross_prefix=powerpc${target_arch#ppc}-linux-gnu-1525 : ${container_image:=debian-$target_arch-cross}1526 : ${container_cross_prefix:=$target_arch-linux-gnu-}1539 if [ "${1%softmmu}" != "$1" ] || test "$target_arch" = "$cpu"; then1540 case "$target_arch:$cpu" in1551 eval "target_cflags=\${cross_cc_cflags_$target_arch}"1567 if eval test -n "\"\${cross_cc_$target_arch}\""; the[all...]
3743 target_arch = {}4358 t = target_arch[target_base_arch].apply(config_target, strict: false)3742 target_arch = {} global() variable
13 target_arch += {'sh4': sh4_ss}
14 target_arch += {'tricore': tricore_ss}
15 target_arch += {'rx': rx_ss}
20 target_arch += {'alpha': alpha_ss}
19 target_arch += {'microblaze': microblaze_ss}
19 target_arch += {'avr': avr_ss}
22 target_arch += {'hppa': hppa_ss}
21 target_arch += {'mips': mips_ss}
21 target_arch += {'m68k': m68k_ss}
24 target_arch += {'openrisc': openrisc_ss}
22 target_arch += {'loongarch': loongarch_ss}
26 target_arch += {'xtensa': xtensa_ss}
24 target_arch += {'sparc': sparc_ss}
42 target_arch += {'s390x': s390x_ss}
36 target_arch += {'i386': i386_ss}
44 target_arch += {'riscv': riscv_ss}
59 target_arch += {'ppc': ppc_ss}
54 target_arch += {'arm': arm_ss}
1518 unsigned int target_arch; in print_insn_sh() local1524 target_arch = arch_sh1; in print_insn_sh()1527 target_arch = arch_sh4; in print_insn_sh()1537 target_arch = arch_sh4; in print_insn_sh()1594 && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up)) in print_insn_sh()1637 if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch)) in print_insn_sh()1799 if (target_arch == arch_sh2a in print_insn_sh()
400 target_arch += {'hexagon': hexagon_ss}
272 of the ``target_arch`` and ``target_system_arch``, which are used respectively278 target_arch += {'arm': arm_ss}