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Searched refs:t5 (Results 1 – 13 of 13) sorted by relevance

/qemu/include/exec/
H A Dhelper-gen.h.inc63 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
67 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \
72 dh_arg(t4, 4), dh_arg(t5, 5)); \
75 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \
79 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \
84 dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \
87 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
91 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
97 dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
H A Dhelper-proto.h.inc40 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
42 dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR;
44 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \
46 dh_ctype(t4), dh_ctype(t5), \
49 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
51 dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
H A Dhelper-head.h.inc140 #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \
141 DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
142 #define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
143 DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
144 #define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
145 DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
/qemu/target/mips/tcg/
H A Dmxu_translate.c1364 TCGv t0, t1, t2, t3, t4, t5, t6, t7; in gen_mxu_q8mul_mac() local
1372 t5 = tcg_temp_new(); in gen_mxu_q8mul_mac()
1400 tcg_gen_extract_tl(t5, t7, 8, 8); in gen_mxu_q8mul_mac()
1405 tcg_gen_mul_tl(t1, t1, t5); in gen_mxu_q8mul_mac()
1411 gen_load_mxu_gpr(t5, XRa); in gen_mxu_q8mul_mac()
1421 tcg_gen_extract_tl(t6, t5, 0, 16); in gen_mxu_q8mul_mac()
1422 tcg_gen_extract_tl(t7, t5, 16, 16); in gen_mxu_q8mul_mac()
1446 TCGv t0, t1, t2, t3, t4, t5, t6, t7; in gen_mxu_q8madl() local
1454 t5 = tcg_temp_new(); in gen_mxu_q8madl()
1473 tcg_gen_extract_tl(t5, t7, 8, 8); in gen_mxu_q8madl()
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_fp0_sqrt.S8 .macro sqrt_seq r, a, y, t1, hn, h2, t5, h
20 const.s \t5, 0
23 maddn.s \t5, \y, \hn
27 maddn.s \hn, \t5, \y
/qemu/common-user/host/mips/
H A Dsafe-syscall.inc.S70 lw t5, FRAME+28(sp)
74 sw t5, 20(sp)
/qemu/linux-user/riscv/
H A Dtarget_syscall.h42 abi_long t5; member
/qemu/linux-headers/asm-riscv/
H A Dptrace.h55 unsigned long t5; member
/qemu/tests/tcg/loongarch64/system/
H A Dregdef.h27 #define t5 $r17 macro
/qemu/tcg/
H A Dtcg.c2742 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) in tcg_gen_call5() argument
2744 TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; in tcg_gen_call5()
2750 TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) in tcg_gen_call6() argument
2752 TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; in tcg_gen_call6()
2758 TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) in tcg_gen_call7() argument
2760 TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; in tcg_gen_call7()
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc62 "t5",
/qemu/tcg/mips/
H A Dtcg-target.c.inc65 "t5",
/qemu/tcg/riscv/
H A Dtcg-target.c.inc44 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",