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Searched refs:special (Results 1 – 25 of 79) sorted by relevance

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/qemu/hw/mips/
H A Dloongson3_bootp.c108 struct loongson_special_attribute *special = g_special; in init_special_info() local
110 strpadcpy(special->special_name, 64, "2018-05-01", '\0'); in init_special_info()
/qemu/disas/
H A Dmicroblaze.c601 static const char *get_special_name(int special) in get_special_name() argument
603 switch (special) { in get_special_name()
631 if ((special & 0xE000) == REG_PVR_MASK) { in get_special_name()
706 int special; in print_insn_microblaze() local
768 special = get_field_special(inst, op); in print_insn_microblaze()
769 special_name = get_special_name(special); in print_insn_microblaze()
775 op->name, get_field_rd(inst), special ^ REG_PVR_MASK); in print_insn_microblaze()
779 special = get_field_special(inst, op); in print_insn_microblaze()
780 special_name = get_special_name(special); in print_insn_microblaze()
786 op->name, special ^ REG_PVR_MASK, get_field_r1(inst)); in print_insn_microblaze()
/qemu/docs/devel/
H A Ds390-dasd-ipl.rst56 management console. This "Load" procedure crafts a special "Read IPL" ccw in
59 written immediately after the special "Read IPL" ccw, the IPL1 channel program
60 will be executed immediately (the special read ccw has the chaining bit turned
123 Because this channel program can be dynamic, we must use a special algorithm
H A Dqapi-domain.rst11 included with Sphinx, but provides special directives and roles
17 provides a set of special rST directives and cross-referencing roles to
26 never need to write *nor* read these special rST forms. However, in the
46 syntax, and qapi_domain.py is responsible for translating that special
67 to give certain field list entries special meaning and parsing to, for
72 The special parsing and handling of info field lists in Sphinx is provided by
143 :feat fdset: Member ``path`` supports the special "/dev/fdset/N" path
376 you had used the ``:qapi:type:`` role. All of the special syntax below
H A Duefi-vars.rst43 The advantage of the approach is that we do not need a special
H A Ddocs.rst24 put into the documentation. A few special directives are recognised;
H A Dmemory.rst35 You typically initialize these with memory_region_init_ram(). Some special
112 have a special case where you need to manage the migration of
130 are for special cases only, and so they do not automatically
/qemu/scripts/coccinelle/
H A Dreset-type.cocci17 // the special-case transformations needed for the core code and for
19 // special cases are at the end of the file.
/qemu/docs/system/
H A Dkeys.rst.inc1 During the graphical emulation, you can use special key combinations from
H A Dtarget-riscv.rst20 special cases like the ``virt`` board.
H A Dtarget-arm.rst30 by hand, except for special cases like the ``virt`` board.
/qemu/target/i386/tcg/
H A Ddecode-new.h294 X86InsnSpecial special:8; member
H A Ddecode-new.c.inc229 #define nolea .special = X86_SPECIAL_NoLoadEA,
230 #define xchg .special = X86_SPECIAL_Locked,
231 #define lock .special = X86_SPECIAL_HasLock,
232 #define mmx .special = X86_SPECIAL_MMX,
233 #define op0_Rd .special = X86_SPECIAL_Op0_Rd,
234 #define op2_Ry .special = X86_SPECIAL_Op2_Ry,
235 #define avx_movx .special = X86_SPECIAL_AVXExtMov,
236 #define sextT0 .special = X86_SPECIAL_SExtT0,
237 #define zextT0 .special = X86_SPECIAL_ZExtT0,
238 #define op0_Mw .special = X86_SPECIAL_Op0_Mw,
[all …]
/qemu/hw/net/
H A De1000_regs.h291 uint16_t special; member
/qemu/qapi/
H A Dmachine-common.json55 # topology settings (e.g., cache topology), and this special
/qemu/hw/ppc/
H A Dppc440_uc.c756 uint32_t special; member
856 ret = s->special; in dcr_read_pcie()
948 s->special = val; in dcr_write_pcie()
/qemu/docs/specs/
H A Dppc-xive.rst170 the O/S. The O/S acknowledges the interrupt with a special load in the
190 XiveEnDSource is a special source object. It exposes the END ESB MMIOs
/qemu/docs/devel/testing/
H A Dqtest.rst13 clock stepping), with a special purpose "qtest" protocol. Refer to
/qemu/target/arm/tcg/
H A Dm-nocp.decode52 # FP system register accesses: these are a special case because accesses
/qemu/target/tricore/
H A Dcsfr.h.inc7 NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
/qemu/docs/
H A Dqdev-device-use.txt73 * media is special. In the old way, it selects disk vs. CD-ROM with
77 * addr is special, see if=virtio below.
225 * mon:LEGACY-CHARDEV is special: it multiplexes the monitor onto the
H A Dpcie_pci_bridge.txt34 The way of bus number to reserve delivery is special
/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc120 * and it is not possible to special-case more relaxed ordering for
/qemu/tcg/tci/
H A DREADME69 TCI needs special implementation for 32 and 64 bit host, 32 and 64 bit target,
/qemu/ui/
H A Dvnc-enc-zrle.c.inc127 /* Solid tile is a special case */

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