Searched refs:set_idx (Results 1 – 4 of 4) sorted by relevance
| /qemu/hw/gpio/ |
| H A D | aspeed_gpio.c | 352 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, in aspeed_gpio_get_pin_level() argument
358 reg_val = s->sets[set_idx].data_value; in aspeed_gpio_get_pin_level()
363 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, in aspeed_gpio_set_pin_level() argument
366 uint32_t value = s->sets[set_idx].data_value; in aspeed_gpio_set_pin_level()
375 aspeed_gpio_update(s, &s->sets[set_idx], value, in aspeed_gpio_set_pin_level()
376 ~s->sets[set_idx].direction); in aspeed_gpio_set_pin_level()
602 if (reg->set_idx >= agc->nr_gpio_sets) { in aspeed_gpio_read()
608 set = &s->sets[reg->set_idx]; in aspeed_gpio_read()
672 uint32_t set_idx = reg_idx_number / ASPEED_GPIOS_PER_SET; in aspeed_gpio_write_index_mode() local
678 set = &s->sets[set_idx]; in aspeed_gpio_write_index_mode()
[all …]
|
| /qemu/contrib/plugins/ |
| H A D | cache.c | 150 static void lru_update_blk(Cache *cache, int set_idx, int blk_idx) in lru_update_blk() argument
152 CacheSet *set = &cache->sets[set_idx]; in lru_update_blk()
153 set->lru_priorities[blk_idx] = cache->sets[set_idx].lru_gen_counter; in lru_update_blk()
157 static int lru_get_lru_block(Cache *cache, int set_idx) in lru_get_lru_block() argument
161 min_priority = cache->sets[set_idx].lru_priorities[0]; in lru_get_lru_block()
165 if (cache->sets[set_idx].lru_priorities[i] < min_priority) { in lru_get_lru_block()
166 min_priority = cache->sets[set_idx].lru_priorities[i]; in lru_get_lru_block()
|
| /qemu/include/hw/gpio/ |
| H A D | aspeed_gpio.h | 68 uint16_t set_idx; member
|
| /qemu/hw/hyperv/ |
| H A D | hyperv.c | 354 unsigned set_idx; in hyperv_set_event_flag() local
363 set_idx = BIT_WORD(eventno); in hyperv_set_event_flag()
367 if ((qatomic_fetch_or(&flags[set_idx], set_mask) & set_mask) != set_mask) { in hyperv_set_event_flag()
|