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Searched refs:sctrdepth (Results 1 – 4 of 4) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c2525 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrsource()
2564 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrtarget()
2604 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrdata()
4306 *ret_val = env->sctrdepth; in rmw_sctrdepth()
4309 env->sctrdepth = (env->sctrdepth & ~mask) | (new_val & mask); in rmw_sctrdepth()
4313 uint64_t depth = get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_sctrdepth()
4317 env->sctrdepth = set_field(env->sctrdepth, SCTRDEPTH_MASK, depth); in rmw_sctrdepth()
4333 uint32_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_sctrstatus()
H A Dmachine.c317 VMSTATE_UINT32(env.sctrdepth, RISCVCPU),
H A Dcpu.h314 uint32_t sctrdepth; member
H A Dcpu_helper.c1007 depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in riscv_ctr_add_entry()