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Searched refs:satp (Results 1 – 11 of 11) sorted by relevance

/qemu/target/riscv/
H A Dmonitor.c157 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in mem_info_svxx()
158 vm = get_field(env->satp, SATP32_MODE); in mem_info_svxx()
160 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in mem_info_svxx()
161 vm = get_field(env->satp, SATP64_MODE); in mem_info_svxx()
226 if (!(env->satp & SATP32_MODE)) { in hmp_info_mem()
231 if (!(env->satp & SATP64_MODE)) { in hmp_info_mem()
H A Dcpu_helper.c210 satp_mode = get_field(env->satp, SATP32_MODE); in riscv_cpu_virt_mem_enabled()
212 satp_mode = get_field(env->satp, SATP64_MODE); in riscv_cpu_virt_mem_enabled()
637 env->vsatp = env->satp; in riscv_cpu_swap_hypervisor_regs()
638 env->satp = env->satp_hs; in riscv_cpu_swap_hypervisor_regs()
660 env->satp_hs = env->satp; in riscv_cpu_swap_hypervisor_regs()
661 env->satp = env->vsatp; in riscv_cpu_swap_hypervisor_regs()
1123 VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) { in do_svukte_check()
1248 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in get_physical_address()
1249 vm = get_field(env->satp, SATP32_MODE); in get_physical_address()
1251 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in get_physical_address()
[all …]
H A Dcpu.c971 uint8_t satp = satp_mode_from_str(name); in cpu_riscv_get_satp() local
974 value = satp_modes->map & (1 << satp); in cpu_riscv_get_satp()
983 uint8_t satp = satp_mode_from_str(name); in cpu_riscv_set_satp() local
990 satp_modes->map = deposit32(satp_modes->map, satp, 1, value); in cpu_riscv_set_satp()
991 satp_modes->init |= 1 << satp; in cpu_riscv_set_satp()
H A Dmachine.c436 VMSTATE_UINTTL(env.satp, RISCVCPU),
H A Dcpu.h300 target_ulong satp; /* since: priv-1.10.0 */ member
H A Dcsr.c622 static RISCVException satp(CPURISCVState *env, int csrno) in satp() function
4284 *val = env->satp; in read_satp()
4295 env->satp = legalize_xatp(env, env->satp, val); in write_satp()
5977 [CSR_SATP] = { "satp", satp, read_satp, write_satp },
/qemu/hw/riscv/
H A Driscv-iommu.c255 uint64_t satp, gatp, pte; in riscv_iommu_spa_fetch() local
270 satp = get_field(ctx->satp, RISCV_IOMMU_ATP_MODE_FIELD); in riscv_iommu_spa_fetch()
273 en_s = satp != RISCV_IOMMU_DC_FSC_MODE_BARE; in riscv_iommu_spa_fetch()
312 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
332 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
373 satp = PPN_PHYS(get_field(ctx->satp, RISCV_IOMMU_ATP_PPN_FIELD)); in riscv_iommu_spa_fetch()
374 addr = (en_s && en_g) ? satp : iotlb->iova; in riscv_iommu_spa_fetch()
375 base = en_g ? gatp : satp; in riscv_iommu_spa_fetch()
748 fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE); in riscv_iommu_validate_device_ctx()
825 if (get_field(ctx->satp, RISCV_IOMMU_PC_FSC_RESERVED)) { in riscv_iommu_validate_process_ctx()
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H A Driscv-iommu.h109 uint64_t satp; /* S-Stage address translation and protection */ member
/qemu/linux-headers/asm-riscv/
H A Dkvm.h80 unsigned long satp; member
/qemu/target/arm/tcg/
H A Dmve_helper.c1249 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ argument
1254 *satp = true; \
1259 #define DO_SQSHL_OP(N, M, satp) \ argument
1260 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp)
1261 #define DO_UQSHL_OP(N, M, satp) \ argument
1262 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp)
1263 #define DO_SQRSHL_OP(N, M, satp) \ argument
1264 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
1265 #define DO_UQRSHL_OP(N, M, satp) \ argument
1266 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
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/qemu/target/riscv/kvm/
H A Dkvm-cpu.c253 KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)),
704 env->satp = 0; in kvm_riscv_reset_regs_csr()