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Searched refs:rv32 (Results 1 – 6 of 6) sorted by relevance

/qemu/disas/
H A Driscv.h20 rv32, enumerator
H A Driscv.c2558 if (isa == rv32) { in decode_inst_opcode()
2591 if (isa == rv32) { in decode_inst_opcode()
2608 if (isa == rv32) { in decode_inst_opcode()
2685 if (isa == rv32) { in decode_inst_opcode()
2767 if (isa == rv32) { in decode_inst_opcode()
5397 case rv32: in decode_inst_decompress()
5520 return print_insn_riscv(memaddr, info, rv32); in print_insn_riscv32()
/qemu/hw/riscv/
H A Dvirt-acpi-build.c290 bool rv32 = riscv_cpu_is_32bit(cpu); in build_rhct() local
310 if (!rv32 && cpu->cfg.max_satp_mode >= VM_1_10_SV39) { in build_rhct()
370 if (!rv32 && cpu->cfg.max_satp_mode >= VM_1_10_SV39) { in build_rhct()
/qemu/target/riscv/
H A Dcpu.c445 bool rv32 = riscv_cpu_is_32bit(cpu); in get_satp_mode_supported() local
446 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; in get_satp_mode_supported()
831 bool rv32 = riscv_cpu_is_32bit(cpu); in riscv_cpu_satp_mode_finalize() local
870 satp_mode_str(satp_mode_map_max, rv32), in riscv_cpu_satp_mode_finalize()
871 satp_mode_str(cpu->cfg.max_satp_mode, rv32)); in riscv_cpu_satp_mode_finalize()
879 if (!rv32) { in riscv_cpu_satp_mode_finalize()
H A Dcsr.c117 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; in ctr() local
119 if (rv32 && csrno >= CSR_CYCLEH) { in ctr()
1915 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32; in validate_vm() local
1918 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; in validate_vm()
5331 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; in write_mcontext() local
5336 mask = rv32 ? MCONTEXT32_HCONTEXT : MCONTEXT64_HCONTEXT; in write_mcontext()
5339 mask = rv32 ? MCONTEXT32 : MCONTEXT64; in write_mcontext()
/qemu/docs/about/
H A Dremoved-features.rst905 option when using the ``rv32`` or ``rv64`` CPUs.
912 via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
966 special that isn't already done by the default CPUs rv32/rv64.