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Searched refs:rs1 (Results 1 – 25 of 40) sorted by relevance

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/qemu/target/riscv/
H A Dfpu_helper.c120 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h() argument
123 float16 frs1 = check_nanbox_h(env, rs1); in do_fmadd_h()
130 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s() argument
133 float32 frs1 = check_nanbox_s(env, rs1); in do_fmadd_s()
217 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fadd_s() argument
219 float32 frs1 = check_nanbox_s(env, rs1); in helper_fadd_s()
224 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fsub_s() argument
226 float32 frs1 = check_nanbox_s(env, rs1); in helper_fsub_s()
231 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fmul_s() argument
233 float32 frs1 = check_nanbox_s(env, rs1); in helper_fmul_s()
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H A Dcrypto_helper.c30 target_ulong rs1, target_ulong rs2, in aes32_operation() argument
51 res = rs1 ^ mixed; in aes32_operation()
56 target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, in HELPER()
59 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER()
62 target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, in HELPER()
65 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER()
68 target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2, in HELPER()
71 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER()
74 target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2, in HELPER()
77 return aes32_operation(shamt, rs1, rs2, false, false); in HELPER()
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H A Dinsn16.decode56 &r rd rs1 rs2 !extern
57 &i imm rs1 rd !extern
58 &s imm rs1 rs2 !extern
60 &b imm rs2 rs1 !extern
62 &shift shamt rs1 rd !extern
63 &r2 rd rs1 !extern
64 &r2_s rs1 rs2 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
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H A Dbitmanip_helper.c27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER()
33 result ^= (rs1 << i); in HELPER()
40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER()
46 result ^= (rs1 >> (TARGET_LONG_BITS - i - 1)); in HELPER()
58 target_ulong HELPER(brev8)(target_ulong rs1) in HELPER()
60 target_ulong x = rs1; in HELPER()
84 target_ulong HELPER(unzip)(target_ulong rs1) in HELPER()
86 target_ulong x = rs1; in HELPER()
95 target_ulong HELPER(zip)(target_ulong rs1) in HELPER()
97 target_ulong x = rs1; in HELPER()
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H A Dxthead.decode16 %rs1 15:5
26 &r rd rs1 rs2 !extern
27 &r2 rd rs1 !extern
28 &shift shamt rs1 rd !extern
29 &th_bfext msb lsb rs1 rd
31 &th_memidx rd rs1 rs2 imm2
32 &th_meminc rd rs1 imm5 imm2
35 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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H A Dinsn32.decode22 %rs1 15:5
46 &b imm rs2 rs1
47 &i imm rs1 rd
49 &r rd rs1 rs2
50 &r2 rd rs1
51 &r2_s rs1 rs2
52 &s imm rs1 rs2
54 &shift shamt rs1 rd
55 &atomic aq rl rs2 rs1 rd
56 &rmrr vm rd rs1 rs2
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H A DXVentanaCondOps.decode14 %rs1 15:5
18 &r rd rs1 rs2 !extern
21 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
H A Dtranslate.c633 static TCGv get_address(DisasContext *ctx, int rs1, int imm) in get_address() argument
636 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); in get_address()
649 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) in get_address_indexed() argument
652 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); in get_address_indexed()
854 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); in gen_logic_imm_fn()
859 TCGv src1h = get_gprh(ctx, a->rs1); in gen_logic_imm_fn()
875 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); in gen_logic()
881 TCGv src1h = get_gprh(ctx, a->rs1); in gen_logic()
899 TCGv src1 = get_gpr(ctx, a->rs1, ext); in gen_arith_imm_fn()
909 TCGv src1h = get_gprh(ctx, a->rs1); in gen_arith_imm_fn()
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/qemu/tests/tcg/tricore/asm/
H A Dmacros.h102 #define TEST_D_D(insn, num, result, rs1) \ argument
104 LI(DREG_RS1, rs1); \
108 #define TEST_D_D_PSW(insn, num, result, psw, rs1) \ argument
110 LI(DREG_RS1, rs1); \
115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ argument
117 LI(DREG_RS1, rs1); \
124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument
126 LI(DREG_RS1, rs1); \
132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument
134 LI(DREG_RS1, rs1); \
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H A Dtest_insert.S5 # insn num result rs1 imm1 rs2 imm2
9 # insn num result rs1 imm1 imm2 imm3
14 # insn num result rs1 rs2 pos width
18 # insn num result rs1 imm1 rs2_h rs2_l
H A Dtest_dextr.S5 # insn num result rs1 rs2 imm
40 # insn num result rs1 rs2 rs3
/qemu/target/sparc/
H A Dinsns.decode17 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
38 &r_r_ri rd rs1 rs2_or_imm imm:bool
39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
43 @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
44 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
45 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
47 &r_r_r rd rs1 rs2
48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
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H A Dtranslate.c2706 if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) { in TRANS()
2750 int rs1, bool imm, int rs2_or_imm) in do_tcc() argument
2767 if (rs1 == 0 && (imm || rs2_or_imm == 0)) { in do_tcc()
2771 tcg_gen_trunc_tl_i32(trap, gen_load_gpr(dc, rs1)); in do_tcc()
2807 return do_tcc(dc, a->cond, a->cc, a->rs1, false, a->rs2); in trans_Tcc_r()
2815 return do_tcc(dc, a->cond, 0, a->rs1, true, a->i); in trans_Tcc_i_v7()
2823 return do_tcc(dc, a->cond, a->cc, a->rs1, true, a->i); in trans_Tcc_i_v9()
2870 if (avail_64(dc) && a->rs1 != 0) { in trans_RDY()
3267 if (a->rs1 == 0 && (a->imm || a->rs2_or_imm == 0)) { in do_wr_special()
3270 TCGv src1 = gen_load_gpr(dc, a->rs1); in do_wr_special()
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/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfh.c.inc52 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
75 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
93 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
110 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
127 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
144 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
161 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
177 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
193 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
209 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_rvd.c.inc65 addr = get_address(ctx, a->rs1, a->imm);
89 addr = get_address(ctx, a->rs1, a->imm);
110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
113 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
131 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
149 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
164 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
167 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
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H A Dtrans_rvf.c.inc56 addr = get_address(ctx, a->rs1, a->imm);
78 addr = get_address(ctx, a->rs1, a->imm);
101 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
118 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
135 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
152 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
169 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
185 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
201 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
217 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_rvzfa.c.inc74 tcg_gen_movi_i64(dest, fli_s_table[a->rs1]);
123 tcg_gen_movi_i64(dest, fli_d_table[a->rs1]);
173 tcg_gen_movi_i64(dest, fli_h_table[a->rs1]);
187 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
204 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
221 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
238 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
255 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
272 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
289 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_xthead.c.inc87 * If !zext_offs, then the address is rs1 + (rs2 << imm2).
88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
90 static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
103 return get_address_indexed(ctx, rs1, offs);
110 * alternative encoding: while sh[123] applies the shift to rs1,
162 TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
187 TCGv src1 = get_gpr(ctx, a->rs1, ext);
314 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */
332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */
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H A Dtrans_rvi.c.inc101 * - c.jalr rs1 where rs1 != x5;
105 * - c.jr rs1 where rs1 != x1 and rs1 != x5.
109 * - c.jr rs1 where rs1 == x1 or rs1 == x5.
124 if ((a->rd == 1 && a->rs1 != 5) || (a->rd == 5 && a->rs1 != 1)) {
126 } else if (a->rd == 0 && a->rs1 != 1 && a->rs1 != 5) {
128 } else if ((a->rs1 == 1 || a->rs1 == 5) && (a->rd != 1 && a->rd != 5)) {
130 } else if ((a->rs1 == 1 && a->rd == 5) || (a->rs1 == 5 && a->rd == 1)) {
147 tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
176 * return from functions (i.e. rs1 == xRA || rs1 == xT0) are not
178 * branch are not tracked. rs1 == xT2 is a sw guarded branch.
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H A Dtrans_rvzicbo.c.inc34 TCGv src = get_address(ctx, a->rs1, 0);
43 TCGv src = get_address(ctx, a->rs1, 0);
52 TCGv src = get_address(ctx, a->rs1, 0);
61 TCGv src = get_address(ctx, a->rs1, 0);
H A Dtrans_rvv.c.inc185 static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
195 if (rd == 0 && rs1 == 0) {
198 } else if (rs1 == 0) {
202 s1 = get_gpr(s, rs1, EXT_ZERO);
238 return do_vsetvl(s, a->rd, a->rs1, s2);
244 return do_vsetvl(s, a->rd, a->rs1, s2);
249 TCGv s1 = tcg_constant_tl(a->rs1);
687 static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
697 base = get_gpr(s, rs1, EXT_NONE);
769 return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
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H A Dtrans_rvbf16.c.inc43 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
58 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
124 vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm) &&
125 vext_check_input_eew(ctx, a->rd, sew + 1, a->rs1, sew, a->vm) &&
136 vreg_ofs(ctx, a->rs1),
163 return opfvf_trans(a->rd, a->rs1, a->rs2, data,
H A Dtrans_rvzicfiss.c.inc39 TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
40 tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);
100 src1 = get_address(ctx, a->rs1, 0);
125 src1 = get_address(ctx, a->rs1, 0);
/qemu/disas/
H A Driscv.c4565 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4570 dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4575 dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4580 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4586 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4592 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4598 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4604 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4610 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
4616 dec->rs1 = operand_rs1(inst); in decode_inst_operands()
[all …]
/qemu/tests/tcg/mips/user/isa/r5900/
H A Dtest_r5900_mflohi1.c12 int32_t rs1 = 32452867, rt1 = 49979687; in main() local
27 "r" (rs1), "r" (rt1)); in main()

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