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Searched refs:rr (Results 1 – 24 of 24) sorted by relevance

/qemu/target/avr/
H A Ddisas.c140 INSN(ADD, "r%d, r%d", a->rd, a->rr)
141 INSN(ADC, "r%d, r%d", a->rd, a->rr)
143 INSN(SUB, "r%d, r%d", a->rd, a->rr)
145 INSN(SBC, "r%d, r%d", a->rd, a->rr)
148 INSN(AND, "r%d, r%d", a->rd, a->rr)
150 INSN(OR, "r%d, r%d", a->rd, a->rr)
152 INSN(EOR, "r%d, r%d", a->rd, a->rr)
157 INSN(MUL, "r%d, r%d", a->rd, a->rr)
158 INSN(MULS, "r%d, r%d", a->rd, a->rr)
159 INSN(MULSU, "r%d, r%d", a->rd, a->rr)
[all …]
H A Dinsn.decode27 %rr 9:1 0:4
42 &rd_rr rd rr
45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
48 @fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b
71 MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a
104 SBRC 1111 110 rr:5 0 bit:3
105 SBRS 1111 111 rr:5 0 bit:3
125 MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d
138 STX1 1001 001 rr:5 1100
139 STX2 1001 001 rr:5 1101
[all …]
H A Dtranslate.c300 TCGv Rr = cpu_r[a->rr]; in trans_ADD()
323 TCGv Rr = cpu_r[a->rr]; in trans_ADC()
385 TCGv Rr = cpu_r[a->rr]; in trans_SUB()
433 TCGv Rr = cpu_r[a->rr]; in trans_SBC()
532 TCGv Rr = cpu_r[a->rr]; in trans_AND()
572 TCGv Rr = cpu_r[a->rr]; in trans_OR()
611 TCGv Rr = cpu_r[a->rr]; in trans_EOR()
719 TCGv Rr = cpu_r[a->rr]; in trans_MUL()
744 TCGv Rr = cpu_r[a->rr]; in trans_MULS()
775 TCGv Rr = cpu_r[a->rr]; in trans_MULSU()
[all …]
/qemu/target/loongarch/
H A Dinsns.decode22 &rr rd rj
60 @rr .... ........ ..... ..... rj:5 rd:5 &rr
178 ext_w_h 0000 00000000 00000 10110 ..... ..... @rr
179 ext_w_b 0000 00000000 00000 10111 ..... ..... @rr
180 clo_w 0000 00000000 00000 00100 ..... ..... @rr
181 clz_w 0000 00000000 00000 00101 ..... ..... @rr
182 cto_w 0000 00000000 00000 00110 ..... ..... @rr
183 ctz_w 0000 00000000 00000 00111 ..... ..... @rr
184 clo_d 0000 00000000 00000 01000 ..... ..... @rr
185 clz_d 0000 00000000 00000 01001 ..... ..... @rr
[all …]
H A Ddisas.c356 INSN(clo_w, rr) in INSN() argument
357 INSN(clz_w, rr) in INSN()
358 INSN(cto_w, rr) in INSN()
359 INSN(ctz_w, rr) in INSN()
360 INSN(clo_d, rr) in INSN()
361 INSN(clz_d, rr) in INSN()
362 INSN(cto_d, rr) in INSN()
363 INSN(ctz_d, rr) in INSN()
364 INSN(revb_2h, rr) in INSN()
365 INSN(revb_4h, rr) in INSN()
[all …]
/qemu/replay/
H A Dreplay.c396 const char *rr; in replay_configure() local
407 rr = qemu_opt_get(opts, "rr"); in replay_configure()
408 if (!rr) { in replay_configure()
411 } else if (!strcmp(rr, "record")) { in replay_configure()
413 } else if (!strcmp(rr, "replay")) { in replay_configure()
416 error_report("Invalid icount rr option: %s", rr); in replay_configure()
/qemu/target/arm/tcg/
H A Da64.decode32 &rr rd rn
703 @rr . .......... ..... ...... rn:5 rd:5 &rr
709 REV64 1 10 11010110 00000 000011 ..... ..... @rr
1376 FJCVTZS 0 0011110 01 111110 000000 ..... ..... @rr
1378 FMOV_ws 0 0011110 00 100110 000000 ..... ..... @rr
1379 FMOV_sw 0 0011110 00 100111 000000 ..... ..... @rr
1381 FMOV_xd 1 0011110 01 100110 000000 ..... ..... @rr
1382 FMOV_dx 1 0011110 01 100111 000000 ..... ..... @rr
1385 FMOV_xu 1 0011110 10 101110 000000 ..... ..... @rr
1386 FMOV_ux 1 0011110 10 101111 000000 ..... ..... @rr
[all …]
H A Dt16.decode28 &rr !extern rd rm
217 @rdm .... .... .. rm:3 rd:3 &rr
H A Da32.decode33 &rr rd rm
226 @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr
H A Dt32.decode30 &rr !extern rd rm
268 @rdm .... .... .... .... .... rd:4 .... rm:4 &rr
/qemu/tests/tcg/arm/
H A DMakefile.softmmu-target66 -icount shift=5$(COMMA)rr=record$(COMMA)rrfile=record.bin \
74 -icount shift=5$(COMMA)rr=replay$(COMMA)rrfile=record.bin \
/qemu/docs/system/
H A Dreplay.rst38 -icount shift=auto,rr=record,rrfile=replay.bin \\
49 -icount shift=auto,rr=replay,rrfile=replay.bin \\
56 The only difference with recording is changing the rr option
127 -icount shift=auto,rr=record,rrfile=replay.bin,rrsnapshot=snapshot_name
153 -icount shift=auto,rr=replay,rrfile=record.bin,rrsnapshot=init \\
154 -net none -drive file=empty.qcow2,if=none,id=rr
/qemu/hw/core/
H A Dqdev-properties-system.c738 ReservedRegion *rr = object_field_prop_ptr(obj, prop); in get_reserved_region() local
744 range_lob(&rr->range), range_upb(&rr->range), rr->type); in get_reserved_region()
754 ReservedRegion *rr = object_field_prop_ptr(obj, prop); in set_reserved_region() local
784 range_set_bounds(&rr->range, lob, upb); in set_reserved_region()
786 ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type); in set_reserved_region()
/qemu/tests/tcg/aarch64/
H A DMakefile.softmmu-target79 -icount shift=5$(COMMA)rr=record$(COMMA)rrfile=record.bin \
87 -icount shift=5$(COMMA)rr=replay$(COMMA)rrfile=record.bin \
/qemu/accel/tcg/
H A Dmeson.build36 'tcg-accel-ops-rr.c',
/qemu/target/rx/
H A Dinsns.decode24 &rr rd rs
43 @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0
61 @b3_rd_rs .... .... .... .... rs:4 rd:4 &rr
62 @b3_rs_rd .... .... .... .... rd:4 rs:4 &rr
/qemu/docs/specs/
H A Dedu.rst47 - ``rr`` -- minor version
/qemu/hw/audio/
H A Dfmopl.c431 int rr = v & 0x0f; in set_sl_rr() local
435 SLOT->RR = &OPL->DR_TABLE[rr<<2]; in set_sl_rr()
/qemu/target/mips/tcg/
H A Dmicromips_translate.c.inc1621 int rt, rs, rd, rr;
1632 rr = (ctx->opcode >> 6) & 0x1f;
1794 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
1805 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
1923 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
/qemu/hw/display/
H A Dtrace-events196 dm163_refresh_rate(uint32_t rr) "refresh rate %d"
/qemu/target/riscv/
H A Dinsn32.decode1040 # zicfiss instruction carved out of mop.rr
/qemu/docs/devel/
H A Dqapi-domain.rst241 "mode": "play", "filename": "log.rr", "icount": 220414 }
/qemu/target/hppa/
H A Dtranslate.c2216 unsigned rr = a->r; in trans_mtsp() local
2226 tcg_gen_shli_i64(tmp, load_gpr(ctx, rr), 32); in trans_mtsp()
/qemu/
H A Dqemu-options.hx4920 …"-icount [shift=N|auto][,align=on|off][,sleep=on|off][,rr=record|replay,rrfile=<filename>[,rrsnaps…
4926 ``-icount [shift=N|auto][,align=on|off][,sleep=on|off][,rr=record|replay,rrfile=filename[,rrsnapsho…
4960 When the ``rr`` option is specified deterministic record/replay is