Home
last modified time | relevance | path

Searched refs:rl (Results 1 – 25 of 27) sorted by relevance

12

/qemu/tests/unit/
H A Dtest-mul64.c15 uint64_t rh, rl; member
43 uint64_t rl, rh; in test_u() local
44 mulu64(&rl, &rh, test_u_data[i].a, test_u_data[i].b); in test_u()
45 g_assert_cmpuint(rl, ==, test_u_data[i].rl); in test_u()
55 uint64_t rl, rh; in test_s() local
56 muls64(&rl, &rh, test_s_data[i].a, test_s_data[i].b); in test_s()
57 g_assert_cmpuint(rl, ==, test_s_data[i].rl); in test_s()
/qemu/target/riscv/
H A Dm128_helper.c48 target_ulong rl, rh; in HELPER() local
52 rl = ul; in HELPER()
56 rl = int128_getlo(r); in HELPER()
61 return rl; in HELPER()
93 target_ulong rh, rl; in HELPER() local
97 rl = ul; in HELPER()
101 rl = int128_getlo(r); in HELPER()
106 return rl; in HELPER()
H A Dinsn32.decode55 &atomic aq rl rs2 rs1 rd
75 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
76 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
H A Dtranslate.c428 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) in gen_set_gpr128() argument
432 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); in gen_set_gpr128()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvm.c.inc50 static void gen_mul_i128(TCGv rl, TCGv rh,
58 tcg_gen_mulu2_tl(rl, rh, rs1l, rs2l);
71 static void gen_mulh_i128(TCGv rl, TCGv rh,
79 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
86 tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h);
87 tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h);
110 static void gen_mulhsu_i128(TCGv rl, TCGv rh,
117 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
121 tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h);
126 TCGv rl = tcg_temp_new();
[all …]
H A Dtrans_rvi.c.inc197 static TCGCond gen_compare_i128(bool bz, TCGv rl,
208 tcg_gen_or_tl(rl, al, ah);
210 tcg_gen_xor_tl(rl, al, bl);
212 tcg_gen_or_tl(rl, rl, rh);
219 tcg_gen_mov_tl(rl, ah);
223 tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
224 tcg_gen_xor_tl(rl, rh, ah);
226 tcg_gen_and_tl(rl, rl, tmp);
227 tcg_gen_xor_tl(rl, rh, rl);
245 tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
[all …]
H A Dtrans_rva.c.inc39 if (a->rl) {
85 TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
/qemu/crypto/
H A Dclmul.c98 uint64_t rl = 0, rh = 0; in clmul_64_gen() local
102 rl = m; in clmul_64_gen()
107 rl ^= (m << i) & mask; in clmul_64_gen()
110 return int128_make128(rl, rh); in clmul_64_gen()
/qemu/bsd-user/
H A Dmain.c245 struct rlimit rl; in adjust_ssize() local
247 if (getrlimit(RLIMIT_STACK, &rl) != 0) { in adjust_ssize()
251 target_maxssiz = MIN(target_maxssiz, rl.rlim_max); in adjust_ssize()
252 target_dflssiz = MIN(MAX(target_dflssiz, rl.rlim_cur), target_maxssiz); in adjust_ssize()
254 rl.rlim_max = target_maxssiz; in adjust_ssize()
255 rl.rlim_cur = target_dflssiz; in adjust_ssize()
256 setrlimit(RLIMIT_STACK, &rl); in adjust_ssize()
/qemu/util/
H A Dhost-utils.c44 LL rl, rm, rn, rh, a0, b0; in mul64() local
50 rl.ll = (uint64_t)a0.l.low * b0.l.low; in mul64()
55 c = (uint64_t)rl.l.high + rm.l.low + rn.l.low; in mul64()
56 rl.l.high = c; in mul64()
62 *plow = rl.ll; in mul64()
/qemu/tcg/
H A Dtcg-op.c1084 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, in tcg_gen_add2_i32() argument
1091 tcg_gen_mov_i32(rl, t0); in tcg_gen_add2_i32()
1100 tcg_gen_mov_i32(rl, t0); in tcg_gen_add2_i32()
1133 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, in tcg_gen_sub2_i32() argument
1140 tcg_gen_mov_i32(rl, t0); in tcg_gen_sub2_i32()
1149 tcg_gen_mov_i32(rl, t0); in tcg_gen_sub2_i32()
1155 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) in tcg_gen_mulu2_i32() argument
1158 tcg_gen_op4_i32(INDEX_op_mulu2, rl, rh, arg1, arg2); in tcg_gen_mulu2_i32()
1163 tcg_gen_mov_i32(rl, t); in tcg_gen_mulu2_i32()
1171 tcg_gen_extr_i64_i32(rl, rh, t0); in tcg_gen_mulu2_i32()
[all …]
H A Doptimize.c2133 TCGArg rl, rh; in fold_multiply2() local
2159 rl = op->args[0]; in fold_multiply2()
2165 tcg_opt_gen_movi(ctx, op, rl, l); in fold_multiply2()
/qemu/include/tcg/
H A Dtcg-op-common.h135 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
137 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
141 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
142 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
143 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
240 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
242 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
246 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
247 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
248 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
/qemu/include/qemu/
H A Dhost-utils.h104 uint64_t rl, rh; in muldiv64_rounding() local
107 rl = (uint64_t)u.l.low * (uint64_t)b; in muldiv64_rounding()
109 rl += c - 1; in muldiv64_rounding()
112 rh += (rl >> 32); in muldiv64_rounding()
114 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; in muldiv64_rounding()
/qemu/linux-user/
H A Dflatload.c150 static void old_reloc(struct lib_info *libinfo, uint32_t rl) in old_reloc() argument
159 offset = rl & 0x3fffffff; in old_reloc()
160 reloc_type = rl >> 30; in old_reloc()
H A Dstrace.c4116 struct target_rlimit64 *rl; in print_rlimit64() local
4118 rl = lock_user(VERIFY_READ, rlim_addr, sizeof(*rl), 1); in print_rlimit64()
4119 if (!rl) { in print_rlimit64()
4123 print_raw_param64("{rlim_cur=%" PRId64, tswap64(rl->rlim_cur), 0); in print_rlimit64()
4124 print_raw_param64("rlim_max=%" PRId64 "}", tswap64(rl->rlim_max), in print_rlimit64()
4126 unlock_user(rl, rlim_addr, 0); in print_rlimit64()
/qemu/target/tricore/
H A Dtranslate.c181 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ argument
187 tcg_gen_extr_i64_i32(rl, rh, ret); \
190 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ argument
194 tcg_gen_extr_i64_i32(rl, rh, ret); \
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) in gen_st_2regs_64() argument
232 tcg_gen_concat_i32_i64(temp, rl, rh); in gen_st_2regs_64()
236 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, in gen_offset_st_2regs() argument
241 gen_st_2regs_64(rh, rl, temp, ctx); in gen_offset_st_2regs()
244 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) in gen_ld_2regs_64() argument
250 tcg_gen_extr_i64_i32(rl, rh, temp); in gen_ld_2regs_64()
[all …]
H A Dop_helper.c115 uint16_t rh, rl; in reverse16() local
117 rl = (uint16_t)((high * 0x0202020202ULL & 0x010884422010ULL) % 1023); in reverse16()
120 return (rh << 8) | rl; in reverse16()
/qemu/disas/
H A Driscv.h208 uint8_t rl; member
H A Driscv.c4647 dec->rl = operand_rl(inst); in decode_inst_operands()
4655 dec->rl = operand_rl(inst); in decode_inst_operands()
5246 if (dec->rl) { in format_inst()
/qemu/target/arm/
H A Dkvm.c772 struct kvm_reg_list rl; in kvm_arm_init_cpreg_list() local
777 rl.n = 0; in kvm_arm_init_cpreg_list()
778 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); in kvm_arm_init_cpreg_list()
782 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); in kvm_arm_init_cpreg_list()
783 rlp->n = rl.n; in kvm_arm_init_cpreg_list()
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc357 TCGv_i64 rh, rl, ah, al, bh, bl;
364 rl = tcg_temp_new_i64();
376 func(rl, rh, al, ah, bl, bh);
379 set_vreg64(rl, a->vd, i * 2);
2127 static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh,
2130 tcg_gen_mulsu2_i64(rl, rh, arg2, arg1);
2138 TCGv_i64 rh, rl, arg1, arg2;
2146 rl = tcg_temp_new_i64();
2154 func(rl, rh, arg1, arg2);
2157 set_vreg64(rl, a->vd, 2 * i);
[all …]
/qemu/fpu/
H A Dsoftfloat-parts.c.inc866 uint64_t dh, dl, rh, rl, sh, sl, uh, ul; /* 128-bit computation */
1012 mul64To128(u64, r64, &rh, &rl);
1013 add128(rh, rl, rh, rl, &rh, &rl);
1016 mul128To256(a->frac_hi, a->frac_lo, rh, rl, &sh, &sl, &discard, &discard);
1017 mul128To256(sh, sl, rh, rl, &dh, &dl, &discard, &discard);
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc2735 TCGv_i64 rl, rh, src1, src2;
2742 rl = tcg_temp_new_i64();
2746 get_avr64(rl, a->rc, false);
2753 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2756 set_avr64(a->vrt, rl, false);
/qemu/hw/usb/
H A Dtrace-events90 usb_ehci_qh_fields(uint32_t addr, int rl, int mplen, int eps, int ep, int devaddr) "QH @ 0x%08x - r…

12