Home
last modified time | relevance | path

Searched refs:riscv_csrrw_debug (Results 1 – 4 of 4) sorted by relevance

/qemu/target/riscv/
H A Dgdbstub.c182 result = riscv_csrrw_debug(env, n, &val, 0, 0); in riscv_gdb_get_csr()
199 result = riscv_csrrw_debug(env, n, NULL, val, -1); in riscv_gdb_set_csr()
H A Dcpu.h846 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
H A Dcpu.c568 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
591 RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0); in riscv_cpu_dump_state()
617 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
H A Dcsr.c5712 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, in riscv_csrrw_debug() function