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Searched refs:riscv_csrrw (Results 1 – 4 of 4) sorted by relevance

/qemu/hw/riscv/
H A Driscv_hart.c74 ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, in csr_call()
/qemu/target/riscv/
H A Dcpu.h843 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
854 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); in riscv_csr_write()
860 riscv_csrrw(env, csrno, &val, 0, 0, 0); in riscv_csr_read()
H A Dop_helper.c74 RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask, GETPC()); in helper_csrw()
85 RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask, GETPC()); in helper_csrrw()
H A Dcsr.c5593 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, in riscv_csrrw() function
5724 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask, 0); in riscv_csrrw_debug()