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Searched refs:riscv_cpu_mxl (Results 1 – 11 of 11) sorted by relevance

/qemu/target/riscv/
H A Ddebug.c81 switch (riscv_cpu_mxl(env)) { in extract_trigger_type()
137 switch (riscv_cpu_mxl(env)) { in build_tdata1()
185 switch (riscv_cpu_mxl(env)) { in tdata1_validate()
228 switch (riscv_cpu_mxl(env)) { in textra_validate()
264 switch (riscv_cpu_mxl(env)) { in textra_validate()
379 switch (riscv_cpu_mxl(env)) { in trigger_textra_match()
424 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_breakpoint_size()
463 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_mcontrol_validate()
505 def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; in type2_breakpoint_insert()
H A Dpmp.c349 pmp_size = 2 << riscv_cpu_mxl(env); in pmp_hart_has_privs()
484 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_write()
510 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_read()
597 riscv_cpu_mxl(env) == MXL_RV64 && in mseccfg_csr_write()
H A Dcsr.c117 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; in ctr()
168 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32()
223 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { in mctr()
241 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32()
259 if (riscv_cpu_mxl(env) != MXL_RV32) { in sscofpmf_32()
277 if (riscv_cpu_mxl(env) != MXL_RV32) { in smcntrpmf_32()
291 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32()
346 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32()
449 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32()
486 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32()
[all …]
H A Dpmu.c296 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr()
428 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_is_of_set()
444 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_set_of_if_clear()
497 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
H A Dmonitor.c156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx()
225 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
H A Dcommon-semi-target.h35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
H A Dinternals.h160 if (riscv_cpu_mxl(env) == MXL_RV32) { in adjust_addr_body()
H A Dcpu.h691 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) macro
693 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
698 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
H A Dcpu_helper.c209 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_cpu_virt_mem_enabled()
1239 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1247 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1257 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1366 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
2184 int mxlen = 16 << riscv_cpu_mxl(env); in riscv_cpu_do_interrupt()
H A Dcpu.c59 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_is_32bit()
774 env->xl = riscv_cpu_mxl(env); in riscv_cpu_reset_hold()
1962 switch (riscv_cpu_mxl(&cpu->env)) { in prop_marchid_set()
2611 switch (riscv_cpu_mxl(env)) { in riscv_gdb_arch_name()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c1577 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { in kvm_riscv_handle_sbi_dbcn()