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Searched refs:rings (Results 1 – 13 of 13) sorted by relevance

/qemu/hw/9pfs/
H A Dxen-9p-backend.c65 Xen9pfsRing *rings; member
144 xen_9pfs_in_sg(&xen_9pfs->rings[pdu->tag % xen_9pfs->num_rings], in xen_9pfs_pdu_vmarshal()
168 xen_9pfs_out_sg(&xen_9pfs->rings[pdu->tag % xen_9pfs->num_rings], in xen_9pfs_pdu_vunmarshal()
187 Xen9pfsRing *ring = &xen_9pfs->rings[pdu->tag % xen_9pfs->num_rings]; in xen_9pfs_init_out_iov_from_pdu()
204 Xen9pfsRing *ring = &xen_9pfs->rings[pdu->tag % xen_9pfs->num_rings]; in xen_9pfs_init_in_iov_from_pdu()
234 Xen9pfsRing *ring = &priv->rings[pdu->tag % priv->num_rings]; in xen_9pfs_push_and_notify()
345 if (xen_9pdev->rings[i].evtchndev != NULL) { in xen_9pfs_disconnect()
346 qemu_set_fd_handler(qemu_xen_evtchn_fd(xen_9pdev->rings[i].evtchndev), in xen_9pfs_disconnect()
348 qemu_xen_evtchn_unbind(xen_9pdev->rings[i].evtchndev, in xen_9pfs_disconnect()
349 xen_9pdev->rings[i].local_port); in xen_9pfs_disconnect()
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/qemu/hw/block/dataplane/
H A Dxen-block.c56 blkif_back_rings_t rings; member
431 &dataplane->rings.native, in xen_block_send_response()
432 dataplane->rings.native.rsp_prod_pvt); in xen_block_send_response()
436 &dataplane->rings.x86_32_part, in xen_block_send_response()
437 dataplane->rings.x86_32_part.rsp_prod_pvt); in xen_block_send_response()
441 &dataplane->rings.x86_64_part, in xen_block_send_response()
442 dataplane->rings.x86_64_part.rsp_prod_pvt); in xen_block_send_response()
452 dataplane->rings.common.rsp_prod_pvt++; in xen_block_send_response()
454 RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&dataplane->rings.common, in xen_block_send_response()
456 if (dataplane->rings.common.rsp_prod_pvt == in xen_block_send_response()
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/qemu/docs/specs/
H A Dvmw_pvscsi-spec.rst17 The shared memory consists of a registers area and a rings area.
19 commands. The rings area is used to transfer data descriptors and SCSI
35 There are three rings in shared memory:
48 used to control rings operation.
86 d. Issue ``PVSCSI_CMD_SETUP_RINGS`` command, provide rings configuration
89 rings configuration as ``struct PVSCSICmdDescSetupMsgRing``
115 and message (if enabled) rings
H A Dppc-spapr-xive.rst228 the O/S and USER register rings make sense. ``W2`` contains the vCPU CAM
H A Drocker.rst160 set of control registers to manage a descriptor ring. The descriptor rings are
161 allocated from contiguous host DMA-able memory and registers specify the rings
170 Descriptor rings' base address must be 8-byte aligned. Descriptors must be
/qemu/hw/net/rocker/
H A Drocker.c68 DescRing **rings; member
475 DescRing *ring = r->rings[ROCKER_RING_EVENT]; in rocker_event_link_changed()
526 DescRing *ring = r->rings[ROCKER_RING_EVENT]; in rocker_event_mac_vlan_seen()
589 return r->rings[(pport - 1) * 2 + 3]; in rocker_get_rx_ring_by_pport()
792 desc_ring_set_base_addr(r->rings[index], in rocker_io_writel()
797 desc_ring_set_size(r->rings[index], val); in rocker_io_writel()
800 if (desc_ring_set_head(r->rings[index], val)) { in rocker_io_writel()
801 rocker_msix_irq(r, desc_ring_get_msix_vector(r->rings[index])); in rocker_io_writel()
805 desc_ring_set_ctrl(r->rings[index], val); in rocker_io_writel()
808 if (desc_ring_ret_credits(r->rings[index], val)) { in rocker_io_writel()
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/qemu/hw/scsi/
H A Dvmw_pvscsi.c54 ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
58 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
119 PVSCSIRingInfo rings; /* Data transfer rings manager */ member
341 pvscsi_ring_cleanup(&s->rings); in pvscsi_reset_state()
395 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); in pvscsi_cmp_ring_put()
405 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); in pvscsi_msg_ring_put()
426 pvscsi_ring_flush_cmp(&s->rings); in pvscsi_process_completion_queue()
578 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { in pvscsi_send_msg()
587 pvscsi_ring_flush_msg(&s->rings); in pvscsi_send_msg()
754 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { in pvscsi_process_io()
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H A Dtrace-events124 pvscsi_ring_init_data(uint32_t txr_len_log2, uint32_t rxr_len_log2) "TX/RX rings logarithms set to …
/qemu/tests/qtest/
H A Dvhost-user-test.c169 uint64_t rings; member
449 s->rings &= ~(0x1ULL << msg.payload.state.index); in chr_read()
495 s->rings |= 0x1ULL << msg.payload.state.index; in chr_read()
754 gboolean overlap = t->src->rings && t->dest->rings; in test_migrate_source_check()
910 while (ctpop64(s->rings) != count) { in wait_for_rings_started()
913 g_assert_cmpint(ctpop64(s->rings), ==, count); in wait_for_rings_started()
974 s->rings = 0; in test_reconnect()
/qemu/hw/net/
H A Dmeson.build62 'fsl_etsec/rings.c',
H A Dsunhme.c686 uint32_t rings = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_RINGSIZE) in sunhme_get_rx_ring_count() local
689 switch (rings) { in sunhme_get_rx_ring_count()
H A Dtrace-events156 e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full"
/qemu/docs/interop/
H A Dvhost-user.rst469 back-end must enable all rings immediately.
471 While processing the rings (whether they are enabled or not), the back-end
573 Once the source has finished migration, rings will be stopped by the
575 further update must be done before rings are restarted.
1133 rings, but some back-ends interpreted it to also discard connection
1136 rings.
1541 Ask the vhost user back-end to disable all rings and reset all