Home
last modified time | relevance | path

Searched refs:rcr (Results 1 – 7 of 7) sorted by relevance

/qemu/hw/net/
H A Dsmc91c111.c43 uint16_t rcr; member
74 VMSTATE_UINT16(rcr, smc91c111_state),
157 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) { in smc91c111_can_receive()
370 s->rcr = 0; in smc91c111_reset()
448 SET_LOW(rcr, value); in smc91c111_writeb()
451 SET_HIGH(rcr, value); in smc91c111_writeb()
452 if (s->rcr & RCR_SOFT_RST) { in smc91c111_writeb()
634 return s->rcr & 0xff; in smc91c111_readb()
636 return s->rcr >> 8; in smc91c111_readb()
805 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) in smc91c111_receive()
[all …]
H A Dmcf_fec.c50 uint32_t rcr; member
309 s->rcr = 0x05ee0001; in mcf_fec_reset()
373 case 0x084: return s->rcr; in mcf_fec_read()
443 s->rcr = value & 0x07ff003f; in mcf_fec_write()
579 if (size > (s->rcr >> 16)) { in mcf_fec_receive()
/qemu/hw/isa/
H A Dpiix.c172 d->rcr = 0; in piix_reset()
202 s->rcr = 0; in piix4_post_load()
225 return (piix3->rcr != 0); in piix3_rcr_needed()
234 VMSTATE_UINT8(rcr, PIIXState),
264 VMSTATE_UINT8_V(rcr, PIIXState, 3),
277 d->rcr = val & 2; /* keep System Reset type only */ in rcr_write()
284 return d->rcr; in rcr_read()
/qemu/include/hw/southbridge/
H A Dpiix.h66 uint8_t rcr; member
/qemu/hw/misc/
H A Dnpcm_clk.c938 uint32_t rcr; in npcm7xx_clk_perform_watchdog_reset() local
941 rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n]; in npcm7xx_clk_perform_watchdog_reset()
942 if (rcr & NPCM7XX_CLK_WDRCR_CA9C) { in npcm7xx_clk_perform_watchdog_reset()
947 __func__, rcr); in npcm7xx_clk_perform_watchdog_reset()
/qemu/hw/arm/
H A Domap1.c2911 uint16_t rcr[2]; member
2983 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; in omap_mcbsp_source_tick()
3125 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ in omap_mcbsp_read()
3155 return s->rcr[1]; in omap_mcbsp_read()
3157 return s->rcr[0]; in omap_mcbsp_read()
3265 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3268 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3412 memset(&s->rcr, 0, sizeof(s->rcr)); in omap_mcbsp_reset()
/qemu/tests/tcg/i386/
H A Dtest-i386.c146 #define OP rcr