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Searched refs:ori (Results 1 – 19 of 19) sorted by relevance

/qemu/tests/tcg/loongarch64/system/
H A Dboot.S39 ori t0, t2, 0x1e5
49 ori t0, t0, 0x1e0
/qemu/tests/qtest/migration/ppc64/
H A Da-b-kernel.S40 ori %r20,%r20,PPC_TEST_MEM_START@l
42 ori %r9,%r9,PPC_TEST_MEM_END@l
/qemu/pc-bios/vof/
H A Dentry.S3 ori rn,rn,name##@l
/qemu/hw/ppc/
H A Dpegasos2.c223 OrIRQState *ori = &pm->orirq[i]; in pegasos2_init() local
229 ori, sizeof(*ori), in pegasos2_init()
232 qdev_realize(DEVICE(ori), NULL, &error_fatal); in pegasos2_init()
234 qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]); in pegasos2_init()
236 qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h)); in pegasos2_init()
/qemu/host/include/loongarch64/host/
H A Dbufferiszero.c.inc60 "ori %0,$r0,1\n"
119 "ori %0,$r0,1\n"
/qemu/target/microblaze/
H A Dinsns.decode201 ori 101000 ..... ..... ................ @typeb
H A Dtranslate.c503 DO_TYPEBI(ori, false, tcg_gen_ori_i32) in DO_TYPEA_CFG()
/qemu/target/riscv/
H A Dinsn32.decode153 # cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
154 ori ............ ..... 110 ..... 0010011 @i
/qemu/target/openrisc/
H A Ddisas.c107 INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k)
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_arith.c.inc303 TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
/qemu/disas/
H A Dmicroblaze.c107 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, enumerator
365 …_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc740 D(0xc00c, OIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2020)
741 D(0xc00d, OILF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2000)
742 D(0xa508, OIHH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1030)
743 D(0xa509, OIHL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1020)
744 D(0xa50a, OILH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1010)
745 D(0xa50b, OILL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1000)
H A Dtranslate_vx.c.inc3202 gen_gvec_fn_2i(ori, ES_32, v1, v2, 1ull << 31);
3221 gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc357 /* val fits in uimm12: ori rd, zero, val */
367 /* High bits must be set; load with lu12i.w + optional ori. */
419 /* Load with pcalau12i + ori. */
H A Dtcg-insn-defs.c.inc1826 /* Emits the `ori d, j, uk12` instruction. */
/qemu/target/loongarch/
H A Dinsns.decode152 ori 0000 001110 ............ ..... ..... @rr_ui12
H A Ddisas.c529 INSN(ori, rr_i) in INSN()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc2111 GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori)
/qemu/tcg/ppc/
H A Dtcg-target.c.inc539 #define NOP ORI /* ori 0,0,0 */