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/qemu/target/xtensa/
H A Dxtensa-isa-internal.h106 xtensa_arg_internal *operands; /* Array[num_operands]. */ member
184 xtensa_operand_internal *operands; member
H A Dxtensa-isa.c846 operand_id = iclass->operands[opnd].u.operand_id; in get_operand()
847 return &intisa->operands[operand_id]; in get_operand()
877 if (iclass->operands[opnd].inout == 's') { in xtensa_operand_is_visible()
881 operand_id = iclass->operands[opnd].u.operand_id; in xtensa_operand_is_visible()
882 intop = &intisa->operands[operand_id]; in xtensa_operand_is_visible()
902 inout = iclass->operands[opnd].inout; in xtensa_operand_inout()
/qemu/scripts/qapi/
H A Dexpr.py294 def _check_infix(operator: str, operands: object) -> None:
295 if not isinstance(operands, list):
300 if not operands:
303 for operand in operands:
H A Dcommon.py221 def gen_infix(operator: str, operands: Sequence[Any]) -> str:
222 return operator.join([do_gen(o, True) for o in operands])
/qemu/docs/devel/
H A Dtcg-ops.rst51 variable operands, input variable operands and constant operands.
56 In the textual form, output operands usually come first, followed by
57 input operands, followed by constant operands. The output type is
972 version. Aliases are specified in the input operands as for GCC.
H A Ddecodetree.rst108 pattern and the ``OR`` pattern put their operands into the same named
/qemu/target/arm/tcg/
H A Dneon-dp.decode93 # assembly the operands are listed "backwards", ie in the order
97 # function code. We would otherwise need to manually swap the operands
H A Dmve.decode86 # assembly the operands are listed "backwards", ie in the order
H A Dsve.decode168 # Two register operands with a 6-bit signed immediate.
/qemu/target/hexagon/
H A DREADME65 By convention, the operands are identified by letter
245 VLIW packet semantics differ from serial semantics in that all input operands
/qemu/disas/
H A Dalpha.c53 unsigned char operands[4]; member
1839 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_alpha()
1860 if (opcode->operands[0] != 0) in print_insn_alpha()
1865 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_alpha()
/qemu/target/hexagon/idef-parser/
H A DREADME.rst346 operands are handled and emitted. For example a right shift between signed
348 will be a logical shift. If one of the two operands is signed, and the other
356 ``rvalue``\ s; in that case if one of the two operands is greater than 32 bits
358 two operands. Fortunately, the most critical instructions already feature
/qemu/fpu/
H A Dsoftfloat-parts.c.inc1520 * If both operands are NaNs, a QNaN is returned.
1523 * but unless both operands are NaNs,
1587 /* For two negative operands, invert the magnitude comparison. */
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc46 * For memory-only operands, if the emitter functions wants to rely on
62 * Vector operands
82 * for 256-bit AVX operands, etc. It is used for conversion operations
209 * clearer to write all three operands explicitly, because the
869 * from the first two operands due to the V operand picking higher entries of
906 * There are some mistakes in the operands in the manual, and the load/store/register
916 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
2233 /* First compute size of operands in order to initialize s->rip_offset. */
H A Demit.c.inc230 /* MOST legacy SSE instructions require aligned memory operands, but not all. */
1115 * There are two output operands, so zero OP1's high 128 bits
3406 * RCx operations are invariant modulo 8*operand_size+1. For 8 and 16-bit operands,
/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc1118 /* Load needed operands */
1369 /* operands of same sign, result different sign */
2295 /* Load needed operands and calculate btarget */
2420 /* Load needed operands and calculate btarget */
/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc1272 /* Instruction operands. */
1976 static xtensa_operand_internal operands[] = {
7659 65, operands,
/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc1297 /* Instruction operands. */
2067 static xtensa_operand_internal operands[] = {
9817 70, operands,
/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc1496 /* Instruction operands. */
2418 static xtensa_operand_internal operands[] = {
11357 77, operands,
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1417 /* Swap operands so that we can use LEU/GTU/GT/LE. */
3712 * Facility 45 is a big bin that contains: distinct-operands,
/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc1708 /* Instruction operands. */
2754 static xtensa_operand_internal operands[] = {
14534 94, operands,
/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc1735 /* Instruction operands. */
2681 static xtensa_operand_internal operands[] = {
15196 93, operands,
/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc1654 /* Instruction operands. */
2600 static xtensa_operand_internal operands[] = {
14069 93, operands,
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc764 swap the operands on GTU/LEU. There's no benefit to loading
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc107 * A vector register cannot be used to provide source operands with more than
383 * Check whether a vector register is used to provide source operands with

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