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Searched refs:operand (Results 1 – 20 of 20) sorted by relevance

/qemu/disas/
H A Dalpha.c1841 const struct alpha_operand *operand = alpha_operands + *opindex; in print_insn_alpha() local
1842 if (operand->extract) in print_insn_alpha()
1843 (*operand->extract) (insn, &invalid); in print_insn_alpha()
1867 const struct alpha_operand *operand = alpha_operands + *opindex; in print_insn_alpha() local
1873 if ((operand->flags & AXP_OPERAND_FAKE) != 0) in print_insn_alpha()
1877 if (operand->extract) in print_insn_alpha()
1878 value = (*operand->extract) (insn, (int *) NULL); in print_insn_alpha()
1881 value = (insn >> operand->shift) & ((1 << operand->bits) - 1); in print_insn_alpha()
1882 if (operand->flags & AXP_OPERAND_SIGNED) in print_insn_alpha()
1884 int signbit = 1 << (operand->bits - 1); in print_insn_alpha()
[all …]
/qemu/target/arm/tcg/
H A Dsve.decode99 # Two operand with unused vector element size
102 # Two operand
106 # Two operand with governing predicate, flags setting
110 # Three operand with unused vector element size
113 # Three predicate operand, with governing predicate, flag setting
116 # Three operand, vector element size
130 # Four operand, vector element size
134 # Four operand with unused vector element size
140 # Three operand with "memory" size, aka immediate left shift
143 # Two register operand, with governing predicate, vector element size
[all …]
H A Dmve.decode29 # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
143 # 2-operand, but Qd and Qn share a field. Size is in bit 28, but we
771 # 2-operand FP
H A Dneon-dp.decode99 # which does not have this odd reversed-operand situation.
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc24 * a result, most operand load and writeback is done entirely in common
25 * table-driven code using the same operand type (X86_TYPE_*) and
34 * "v" or "z" sizes. The decoder simply makes them separate operand sizes.
48 * operand. Therefore, M is often replaced by the more specific EM and WM
49 * (respectively selecting an ALU operand, like the operand type E, or a
50 * vector operand like the operand type W).
54 * an additional custom operand type "I_unsigned". Alternatively, the
58 * Finally, a "nop" operand type is used for multi-byte NOPs. It accepts
60 * interpret the operand (like M).
80 * There is a custom size "xh" used to address half of a SSE/AVX operand.
[all …]
H A Dcc_helper_template.h.inc40 #error unhandled operand size
H A Demit.c.inc79 /* Extract memory displacement from the second operand. */
1327 * Extract START, and shift the operand.
1328 * Shifts larger than operand size get zeros.
1337 * operand size get all zeros, length 0 gets all ones.
1690 * - s->T1: addition operand (from decoder)
1692 * - s->cc_srcT: memory operand (lhs for comparison)
1778 * Unlike the memory case, where "the destination operand receives
2530 /* M operand type does not load/store */
2812 /* Careful, operand order is reversed! */
3634 * The input has already been zero-extended upon operand decode.
[all …]
/qemu/target/microblaze/
H A Dinsns.decode156 # operand which is unused. So allow the field to be non-zero but discard
157 # the value and treat as 2-operand insns.
/qemu/scripts/qapi/
H A Dexpr.py303 for operand in operands:
304 _check_if(operand)
/qemu/target/hexagon/
H A DREADME69 The generator uses the operand naming conventions (see large comment in
158 Notice that we also generate a variable named <operand>_off for each operand of
/qemu/fpu/
H A Dsoftfloat-parts.c.inc1503 * if one operand is a QNaN, and the other
1504 * operand is numerical, then return numerical argument.
1521 * If either operand is a SNaN,
1584 /* For differing signs, the negative operand is less. */
/qemu/tcg/i386/
H A Dtcg-target.c.inc783 mode for absolute addresses, ~RM is the size of the immediate operand
988 /* imm8 operand: all output lanes selected from input lane 0. */
1987 /* Emit 1 or 2 operand size prefixes for the standard one byte nop,
3159 /* For small constant 3-operand shift, use LEA. */
3472 /* Note that SHRD outputs to the r/m operand. */
/qemu/tcg/riscv/
H A Dtcg-target.c.inc676 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
677 * second operand.
/qemu/docs/devel/
H A Dtcg-ops.rst920 **Note 1**: Some shortcuts are defined when the last operand is known to be
H A Dqapi-code-gen.rst797 preprocessing directive with an operand generated from that condition:
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1652 * into the separate operand.
/qemu/target/s390x/tcg/
H A Dtranslate_vx.c.inc31 * On s390x, the operand size (oprsz) and the maximum size (maxsz) are
/qemu/tcg/arm/
H A Dtcg-target.c.inc1454 * isn't worth checking for an immediate operand for BIC.
/qemu/tcg/s390x/
H A Dtcg-target.c.inc732 * is the left-shift of the 4th operand.
/qemu/tests/tcg/i386/
H A Dx86.csv35 # distinguished only by operand size, like most arithmetic instructions.
134 # applies when using the specified operand size. It may therefore be necessary to use an
135 # operand size prefix byte to access the instruction.
136 # If two operand tags are listed, the instruction can be used with either of those
137 # operand sizes. An instruction will never list all three operand sizes.