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Searched refs:occ (Results 1 – 4 of 4) sorted by relevance

/qemu/hw/ppc/
H A Dpnv_occ.c57 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) in pnv_occ_set_misc() argument
61 occ->occmisc = val; in pnv_occ_set_misc()
68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); in pnv_occ_set_misc()
71 static void pnv_occ_raise_msg_irq(PnvOCC *occ) in pnv_occ_raise_msg_irq() argument
73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); in pnv_occ_raise_msg_irq()
79 PnvOCC *occ = PNV_OCC(opaque); in pnv_occ_power8_xscom_read() local
85 val = occ->occmisc; in pnv_occ_power8_xscom_read()
97 PnvOCC *occ = PNV_OCC(opaque); in pnv_occ_power8_xscom_write() local
102 pnv_occ_set_misc(occ, occ->occmisc & val); in pnv_occ_power8_xscom_write()
105 pnv_occ_set_misc(occ, occ->occmisc | val); in pnv_occ_power8_xscom_write()
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H A Dpnv.c1469 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); in pnv_chip_power8_instance_init()
1587 object_property_set_link(OBJECT(&chip8->occ), "homer", in pnv_chip_power8_realize()
1589 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { in pnv_chip_power8_realize()
1592 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); in pnv_chip_power8_realize()
1593 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, in pnv_chip_power8_realize()
1598 &chip8->occ.sram_regs); in pnv_chip_power8_realize()
1711 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); in pnv_chip_power9_instance_init()
1907 object_property_set_link(OBJECT(&chip9->occ), "homer", in pnv_chip_power9_realize()
1909 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { in pnv_chip_power9_realize()
1912 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); in pnv_chip_power9_realize()
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/qemu/target/openrisc/
H A Dcpu.c108 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); in openrisc_cpu_reset_hold() local
110 if (occ->parent_phases.hold) { in openrisc_cpu_reset_hold()
111 occ->parent_phases.hold(obj, type); in openrisc_cpu_reset_hold()
171 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); in openrisc_cpu_realizefn() local
187 occ->parent_realize(dev, errp); in openrisc_cpu_realizefn()
278 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); in openrisc_cpu_class_init() local
279 CPUClass *cc = CPU_CLASS(occ); in openrisc_cpu_class_init()
284 &occ->parent_realize); in openrisc_cpu_class_init()
286 &occ->parent_phases); in openrisc_cpu_class_init()
/qemu/include/hw/ppc/
H A Dpnv_chip.h61 PnvOCC occ; member
89 PnvOCC occ; member
123 PnvOCC occ; member