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Searched refs:mw (Results 1 – 7 of 7) sorted by relevance

/qemu/tests/tcg/i386/
H A Dtest-avx.py96 def __init__(self, reg, mw): argument
97 if mw not in [0, 8, 16, 32, 64, 128, 256]:
100 self.mw = mw
101 self.ismem = mw != 0
104 return mem_w(self.mw)
110 def __init__(self, mw): argument
111 if mw not in [0, 32, 64]:
112 raise Exception("Bad mem width: %s" % mw)
113 self.mw = mw
114 self.ismem = mw != 0
[all …]
H A Dtest-mmx.py60 def __init__(self, mw): argument
61 if mw not in [0, 32, 64]:
63 self.mw = mw
64 self.ismem = mw != 0
67 return mem_w(self.mw)
95 def __init__(self, rw, mw): argument
98 if mw not in [0, 8, 16, 32, 64]:
101 self.mw = mw
102 self.ismem = mw != 0
105 return mem_w(self.mw)
[all …]
/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc2741 { "mw", 41, 1, 1,
4397 { { 35 /* mw */ }, 'o' },
4408 { { 35 /* mw */ }, 'o' },
4419 { { 35 /* mw */ }, 'o' },
/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc2919 { "mw", FIELD_w, REGFILE_MR, 1,
/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc2822 { "mw", FIELD_w, REGFILE_MR, 1,
/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc4166 { "mw", FIELD_w, REGFILE_MR, 1,
/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc12282 { "mw", FIELD_w, REGFILE_MR, 1,