Home
last modified time | relevance | path

Searched refs:mvien (Results 1 – 4 of 4) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c2298 *ret_val = env->mvien; in rmw_mvien64()
2301 env->mvien = (env->mvien & ~mask) | (new_val & mask); in rmw_mvien64()
2647 (env->priv == PRV_S && env->mvien & MIP_SEIP && in rmw_xireg_aia()
2931 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { in rmw_xtopei()
3745 (env->mideleg | ~env->mvien)) | MIP_STIP; in rmw_mvip64()
3747 (~env->mideleg & env->mvien); in rmw_mvip64()
3762 alias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()
3763 nalias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()
3980 (~env->mideleg & env->mvien); in rmw_sie64()
4226 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; in rmw_sip64()
[all …]
H A Dcpu_helper.c448 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()
512 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()
734 irqf = env->mvien & env->mvip & env->sie; in riscv_cpu_interrupt()
2170 bool s_injected = env->mvip & (1ULL << cause) & env->mvien && in riscv_cpu_do_interrupt()
H A Dmachine.c432 VMSTATE_UINT64(env.mvien, RISCVCPU),
H A Dcpu.h329 uint64_t mvien; member