Home
last modified time | relevance | path

Searched refs:mstateen (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c58 if (!(env->mstateen[index] & bit)) { in smstateen_acc_ok()
493 static RISCVException mstateen(CPURISCVState *env, int csrno) in mstateen() function
518 if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { in hstateen_pred()
555 if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { in sstateen()
3390 *val = env->mstateen[csrno - CSR_MSTATEEN0]; in read_mstateen()
3400 reg = &env->mstateen[csrno - CSR_MSTATEEN0]; in write_mstateen()
3447 *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; in read_mstateenh()
3457 reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; in write_mstateenh()
3492 *val = env->hstateen[index] & env->mstateen[index]; in read_hstateen()
3504 wr_mask = env->mstateen[index] & mask; in write_hstateen()
[all …]
H A Dmachine.c275 VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
H A Dcpu.h469 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; member