Home
last modified time | relevance | path

Searched refs:msr_mask (Results 1 – 9 of 9) sorted by relevance

/qemu/target/ppc/
H A Dhelper_regs.c137 uint32_t msr_mask; in hreg_compute_hflags_value() local
144 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | in hreg_compute_hflags_value()
158 msr_mask |= 1 << MSR_BE; in hreg_compute_hflags_value()
162 msr_mask |= 1 << MSR_SE; in hreg_compute_hflags_value()
174 msr_mask |= 1 << MSR_VR; in hreg_compute_hflags_value()
178 msr_mask |= 1 << MSR_VSX; in hreg_compute_hflags_value()
241 return hflags | (msr & msr_mask); in hreg_compute_hflags_value()
297 value &= env->msr_mask; in hreg_store_msr()
H A Dcpu_init.c2185 pcc->msr_mask = (1ull << MSR_WE) |
2256 pcc->msr_mask = (1ull << MSR_POW) |
2295 pcc->msr_mask = (1ull << MSR_POW) |
2347 pcc->msr_mask = (1ull << MSR_POW) |
2417 pcc->msr_mask = (1ull << MSR_POW) |
2456 pcc->msr_mask = (1ull << MSR_POW) |
2499 pcc->msr_mask = (1ull << MSR_ILE) | in POWERPC_FAMILY()
2541 pcc->msr_mask = (1ull << MSR_ILE) | in POWERPC_FAMILY()
2596 pcc->msr_mask = (1ull << MSR_POW) | in POWERPC_FAMILY()
2635 pcc->msr_mask = (1ull << MSR_POW) | in POWERPC_FAMILY()
[all …]
H A Dexcp_helper.c371 assert((msr & env->msr_mask) == msr); in powerpc_set_excp_state()
1281 if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB) && in powerpc_excp_books()
1300 if (env->msr_mask & MSR_HVB) { in powerpc_excp_books()
1432 if (env->msr_mask & MSR_HVB) { in powerpc_excp_books()
1538 if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) { in powerpc_excp_books()
H A Darch_dump.c246 if (ppc_interrupts_little_endian(cpu, !!(cpu->env.msr_mask & MSR_HVB))) { in cpu_get_dump_info()
H A Dmisc_helper.c119 if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) && in helper_hfscr_facility_check()
H A Dmachine.c21 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); in post_load_update_msr()
H A Dcpu.h1327 target_ulong msr_mask; member
1506 uint64_t msr_mask; member
/qemu/hw/ppc/
H A Dspapr_nested.c552 regs->msr = l2_state.srr1 & env->msr_mask; in spapr_exit_nested_hv()
555 regs->msr = hsrr1 & env->msr_mask; in spapr_exit_nested_hv()
1628 vcpu->state.msr = env->spr[SPR_SRR1] & env->msr_mask; in exit_nested_store_l2()
1631 vcpu->state.msr = env->spr[SPR_HSRR1] & env->msr_mask; in exit_nested_store_l2()
/qemu/target/arm/tcg/
H A Dtranslate.c2610 static uint32_t msr_mask(DisasContext *s, int flags, int spsr) in msr_mask() function
4542 uint32_t mask = msr_mask(s, a->mask, a->r); in trans_MSR_imm()
4645 uint32_t mask = msr_mask(s, a->mask, a->r); in trans_MSR_reg()