| /qemu/hw/pci-host/ |
| H A D | pnv_phb3_msi.c | 65 static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, uint8_t gen) in phb3_msi_set_p() argument
70 ive_addr = phb3_msi_ive_addr(msi->phb, srcno); in phb3_msi_set_p()
82 static void phb3_msi_set_q(Phb3MsiState *msi, int srcno) in phb3_msi_set_q() argument
87 ive_addr = phb3_msi_ive_addr(msi->phb, srcno); in phb3_msi_set_q()
99 static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool force) in phb3_msi_try_send() argument
101 ICSState *ics = ICS(msi); in phb3_msi_try_send()
105 if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) { in phb3_msi_try_send()
128 phb3_msi_set_q(msi, srcno); in phb3_msi_try_send()
131 phb3_msi_set_p(msi, srcno, gen); in phb3_msi_try_send()
137 phb3_msi_set_q(msi, srcno); in phb3_msi_try_send()
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| H A D | designware.c | 100 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
102 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
103 qemu_set_irq(host->pci.msi, 1); in designware_pcie_root_msi_write()
120 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping()
121 const uint64_t base = root->msi.base; in designware_pcie_root_update_msi_mapping()
122 const bool enable = root->msi.intr[0].enable; in designware_pcie_root_update_msi_mapping()
167 val = extract64(root->msi.base, in designware_pcie_root_config_read()
172 val = root->msi.intr[0].enable; in designware_pcie_root_config_read()
176 val = root->msi.intr[0].mask; in designware_pcie_root_config_read()
180 val = root->msi.intr[0].status; in designware_pcie_root_config_read()
[all …]
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| /qemu/hw/xen/ |
| H A D | xen_pt_msi.c | 69 static inline uint64_t msi_addr64(XenPTMSI *msi) in msi_addr64() argument
71 return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; in msi_addr64()
240 if (!s->msi) { in xen_pt_msi_set_enable()
244 return msi_msix_enable(s, s->msi->ctrl_offset, PCI_MSI_FLAGS_ENABLE, in xen_pt_msi_set_enable()
253 XenPTMSI *msi = s->msi; in xen_pt_msi_setup() local
255 if (msi->initialized) { in xen_pt_msi_setup()
261 rc = msi_msix_setup(s, msi_addr64(msi), msi->data, &pirq, false, 0, true); in xen_pt_msi_setup()
271 msi->pirq = pirq; in xen_pt_msi_setup()
279 XenPTMSI *msi = s->msi; in xen_pt_msi_update() local
282 return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq, in xen_pt_msi_update()
[all …]
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| H A D | xen_pt_config_init.c | 1076 XenPTMSI *msi = s->msi; in xen_pt_msgctrl_reg_init() local
1090 msi->flags |= reg_field; in xen_pt_msgctrl_reg_init()
1091 msi->ctrl_offset = real_offset; in xen_pt_msgctrl_reg_init()
1092 msi->initialized = false; in xen_pt_msgctrl_reg_init()
1093 msi->mapped = false; in xen_pt_msgctrl_reg_init()
1103 XenPTMSI *msi = s->msi; in xen_pt_msgctrl_reg_write() local
1116 msi->flags |= *data & ~PCI_MSI_FLAGS_ENABLE; in xen_pt_msgctrl_reg_write()
1124 if (!msi->initialized) { in xen_pt_msgctrl_reg_write()
1142 msi->initialized = true; in xen_pt_msgctrl_reg_write()
1143 msi->mapped = true; in xen_pt_msgctrl_reg_write()
[all …]
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| /qemu/hw/intc/ |
| H A D | arm_gicv3_its_kvm.c | 47 struct kvm_msi msi; in kvm_its_send_msi() local
59 msi.address_lo = extract64(s->gits_translater_gpa, 0, 32); in kvm_its_send_msi()
60 msi.address_hi = extract64(s->gits_translater_gpa, 32, 32); in kvm_its_send_msi()
61 msi.data = le32_to_cpu(value); in kvm_its_send_msi()
62 msi.flags = KVM_MSI_VALID_DEVID; in kvm_its_send_msi()
63 msi.devid = devid; in kvm_its_send_msi()
64 memset(msi.pad, 0, sizeof(msi.pad)); in kvm_its_send_msi()
66 return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); in kvm_its_send_msi()
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| H A D | riscv_imsic.c | 303 struct kvm_msi msi; in riscv_imsic_write() local
305 msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32); in riscv_imsic_write()
306 msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32); in riscv_imsic_write()
307 msi.data = le32_to_cpu(value); in riscv_imsic_write()
309 kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); in riscv_imsic_write()
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| H A D | apic.c | 920 static void apic_send_msi(MSIMessage *msi) in apic_send_msi() argument
922 uint64_t addr = msi->address; in apic_send_msi()
923 uint32_t data = msi->data; in apic_send_msi()
1089 MSIMessage msi = { .address = addr, .data = val }; in apic_mem_write() local
1090 apic_send_msi(&msi); in apic_mem_write()
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| /qemu/hw/pci-bridge/ |
| H A D | pci_bridge_dev.c | 50 OnOffAuto msi; member
75 bridge_dev->msi = ON_OFF_AUTO_OFF; in pci_bridge_dev_realize()
83 if (bridge_dev->msi != ON_OFF_AUTO_OFF) { in pci_bridge_dev_realize()
90 if (err && bridge_dev->msi == ON_OFF_AUTO_ON) { in pci_bridge_dev_realize()
97 assert(!local_err || bridge_dev->msi == ON_OFF_AUTO_AUTO); in pci_bridge_dev_realize()
175 DEFINE_PROP_ON_OFF_AUTO(PCI_BRIDGE_DEV_PROP_MSI, PCIBridgeDev, msi,
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| H A D | pcie_pci_bridge.c | 26 OnOffAuto msi; member
70 if (pcie_br->msi != ON_OFF_AUTO_OFF) { in OBJECT_DECLARE_SIMPLE_TYPE()
74 if (pcie_br->msi != ON_OFF_AUTO_ON) { in OBJECT_DECLARE_SIMPLE_TYPE()
127 DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
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| /qemu/hw/ppc/ |
| H A D | spapr_pci.c | 282 SpaprPciMsi *msi; in rtas_ibm_change_msi() local
330 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); in rtas_ibm_change_msi()
334 if (!msi) { in rtas_ibm_change_msi()
346 g_hash_table_remove(phb->msi, &config_addr); in rtas_ibm_change_msi()
408 if (msi) { in rtas_ibm_change_msi()
409 g_hash_table_remove(phb->msi, &config_addr); in rtas_ibm_change_msi()
417 msi = g_new(SpaprPciMsi, 1); in rtas_ibm_change_msi()
418 msi->first_irq = irq; in rtas_ibm_change_msi()
419 msi->num = req_num; in rtas_ibm_change_msi()
422 g_hash_table_insert(phb->msi, config_addr_key, msi); in rtas_ibm_change_msi()
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| H A D | e500.c | 395 char *msi; in ppce500_load_device_tree() local
593 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); in ppce500_load_device_tree()
594 qemu_fdt_add_subnode(fdt, msi); in ppce500_load_device_tree()
595 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); in ppce500_load_device_tree()
596 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); in ppce500_load_device_tree()
598 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); in ppce500_load_device_tree()
599 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); in ppce500_load_device_tree()
600 qemu_fdt_setprop_cells(fdt, msi, "interrupts", in ppce500_load_device_tree()
609 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); in ppce500_load_device_tree()
610 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); in ppce500_load_device_tree()
[all …]
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| /qemu/hw/i386/xen/ |
| H A D | xen_apic.c | 74 static void xen_send_msi(MSIMessage *msi) in xen_send_msi() argument
76 xen_hvm_inject_msi(msi->address, msi->data); in xen_send_msi()
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| /qemu/hw/usb/ |
| H A D | hcd-xhci-pci.c | 147 if (s->msi != ON_OFF_AUTO_OFF) { in usb_xhci_pci_realize()
154 if (ret && s->msi == ON_OFF_AUTO_ON) { in usb_xhci_pci_realize()
161 assert(!err || s->msi == ON_OFF_AUTO_AUTO); in usb_xhci_pci_realize()
220 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
272 s->msi = ON_OFF_AUTO_OFF; in qemu_xhci_instance_init()
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| H A D | hcd-xhci-pci.h | 41 OnOffAuto msi; member
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| /qemu/scripts/ |
| H A D | extract-vsssdk-headers | 29 tail -c +$(($offset+1)) -- "$1" > vsssdk.msi
32 msiextract -C $tmpdir vsssdk.msi
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| /qemu/include/hw/pci-host/ |
| H A D | designware.h | 80 DesignwarePCIEMSI msi; member
96 qemu_irq msi; member
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| H A D | spapr.h | 70 GHashTable *msi; member
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| /qemu/docs/system/i386/ |
| H A D | kvm-pv.rst | 24 ``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split
77 ``kvm-msi-ext-dest-id``
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| /qemu/hw/audio/ |
| H A D | intel-hda.c | 198 OnOffAuto msi; member
261 bool msi = msi_enabled(&d->pci); in intel_hda_update_irq() local
271 level, msi ? "msi" : "intx"); in intel_hda_update_irq()
272 if (msi) { in intel_hda_update_irq()
1103 if (d->msi != ON_OFF_AUTO_OFF) { in intel_hda_realize()
1109 if (ret && d->msi == ON_OFF_AUTO_ON) { in intel_hda_realize()
1116 assert(!err || d->msi == ON_OFF_AUTO_AUTO); in intel_hda_realize()
1219 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
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| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 439 enable-msi-hole;
548 MSI: ppc4xx-msi@C10000000 {
549 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
552 msi-data = <0x00000000>;
553 msi-mask = <0x44440000>;
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| /qemu/hw/pci/ |
| H A D | meson.build | 3 'msi.c',
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| /qemu/hw/scsi/ |
| H A D | mptsas.h | 36 OnOffAuto msi; member
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| /qemu/accel/kvm/ |
| H A D | kvm-all.c | 27 #include "hw/pci/msi.h"
2148 struct kvm_msi msi; in kvm_irqchip_send_msi()
2150 msi.address_lo = (uint32_t)msg.address; in kvm_irqchip_send_msi()
2151 msi.address_hi = msg.address >> 32; in kvm_irqchip_send_msi()
2152 msi.data = le32_to_cpu(msg.data); in kvm_irqchip_send_msi()
2153 msi.flags = 0; in kvm_irqchip_send_msi()
2154 memset(msi.pad, 0, sizeof(msi.pad)); in kvm_irqchip_send_msi()
2156 return kvm_vm_ioctl(s, KVM_SIGNAL_MSI, &msi); in kvm_irqchip_send_msi()
2186 kroute.u.msi in kvm_irqchip_add_msi_route()
2147 struct kvm_msi msi; kvm_irqchip_send_msi() local
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| /qemu/include/hw/ppc/ |
| H A D | openpic.h | 169 OpenPICMSI msi[MAX_MSI]; member
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| /qemu/qga/ |
| H A D | meson.build | 157 output: 'qemu-ga-@0@.msi'.format(host_arch),
171 alias_target('msi', qga_msi) run
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