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Searched refs:misa_ext (Results 1 – 12 of 12) sorted by relevance

/qemu/target/riscv/
H A Dgdbstub.c117 if (env->misa_ext & RVD) { in riscv_gdb_get_fpu()
120 if (env->misa_ext & RVF) { in riscv_gdb_get_fpu()
347 if (env->misa_ext & RVD) { in riscv_cpu_register_gdb_regs_for_features()
351 } else if (env->misa_ext & RVF) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.c361 env->misa_ext_mask = env->misa_ext = ext; in riscv_cpu_set_misa_ext()
1127 env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext; in riscv_cpu_init()
2010 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
2043 .misa_ext = RVS,
2064 .misa_ext = RVV,
2094 .misa_ext = RVS,
2742 mcc->def->misa_ext |= def->misa_ext; in riscv_cpu_class_base_init()
2785 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_string()
2803 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_extensions_list()
2935 .misa_ext = RVI | RVM | RVA | RVC | RVU,
[all …]
H A Dcpu.h84 uint32_t misa_ext; member
234 uint32_t misa_ext; /* current extensions */ member
546 uint32_t misa_ext; member
571 return (env->misa_ext & ext) != 0; in riscv_has_ext()
792 uint32_t misa_ext) in riscv_cpu_allow_16bit_insn() argument
798 return misa_ext & RVC; in riscv_cpu_allow_16bit_insn()
H A Dtranslate.c64 uint32_t misa_ext; member
125 return ctx->misa_ext & ext; in has_ext()
610 ctx->misa_ext)) { in gen_jal()
1268 ctx->misa_ext = env->misa_ext; in riscv_tr_init_disas_context()
H A Dop_helper.c286 env->misa_ext) && (retpc & 0x3)) { in helper_sret()
366 env->misa_ext) && (retpc & 0x3)) { in check_ret_from_m_mode()
H A Dmachine.c421 VMSTATE_UINT32(env.misa_ext, RISCVCPU),
H A Dcsr.c2083 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); in read_misa_i128()
2105 *val = misa | env->misa_ext; in read_misa()
2126 uint32_t orig_misa_ext = env->misa_ext; in write_misa()
2149 if (val == env->misa_ext) { in write_misa()
2153 env->misa_ext = val; in write_misa()
2159 env->misa_ext, orig_misa_ext); in write_misa()
2161 env->misa_ext = orig_misa_ext; in write_misa()
2166 if (!(env->misa_ext & RVF)) { in write_misa()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c79 env->misa_ext |= bit; in riscv_cpu_write_misa_bit()
82 env->misa_ext &= ~bit; in riscv_cpu_write_misa_bit()
913 if (!(profile->misa_ext & bit)) { in riscv_cpu_validate_profile()
1008 !(env->misa_ext & misa_bits[i])) { in cpu_enable_implied_rule()
1012 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); in cpu_enable_implied_rule()
1236 prev_val = env->misa_ext & misa_bit; in cpu_set_misa_ext_cfg()
1271 value = env->misa_ext & misa_bit; in cpu_get_misa_ext_cfg()
1382 if (!(profile->misa_ext & bit)) { in cpu_set_profile()
1582 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); in riscv_init_max_cpu_extensions()
/qemu/linux-user/riscv/
H A Dcpu_loop.c107 if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { in target_cpu_copy_regs()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c235 env->misa_ext &= ~misa_bit; in kvm_riscv_update_cpu_misa_ext()
1047 env->misa_ext = env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc156 ctx->misa_ext)) {
307 ctx->misa_ext) &&
/qemu/linux-user/
H A Delfload.c1871 return cpu->env.misa_ext & mask; in get_elf_hwcap()