Searched refs:menvcfg (Results 1 – 6 of 6) sorted by relevance
81 return env->menvcfg & MENVCFG_LPE; in cpu_get_fcfien()87 return env->menvcfg & MENVCFG_LPE; in cpu_get_fcfien()116 return env->menvcfg & MENVCFG_SSE; in cpu_get_bcfien()133 return (env->menvcfg & MENVCFG_DTE) != 0; in riscv_env_smode_dbltrp_enabled()160 return get_field(env->menvcfg, MENVCFG_PMM); in riscv_pm_get_pmm()171 return get_field(env->menvcfg, MENVCFG_PMM); in riscv_pm_get_pmm()1308 bool pbmte = env->menvcfg & MENVCFG_PBMTE; in get_physical_address()1311 bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade; in get_physical_address()2296 bool dte = (env->menvcfg & MENVCFG_DTE) != 0; in riscv_cpu_do_interrupt()
599 get_field(env->menvcfg, MENVCFG_STCE))) { in sstc()1604 get_field(env->menvcfg, MENVCFG_CDE) && in read_scountovf()2746 !get_field(env->menvcfg, MENVCFG_CDE)) { in rmw_xireg_cd()3172 *val = env->menvcfg; in read_menvcfg()3210 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); in write_menvcfg()3217 *val = env->menvcfg >> 32; in read_menvcfgh()3238 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); in write_menvcfgh()3279 get_field(env->menvcfg, MENVCFG_SSE) && in write_senvcfg()3309 HENVCFG_DTE) | env->menvcfg); in read_henvcfg()3325 mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | in write_henvcfg()[all …]
296 VMSTATE_UINT64(env.menvcfg, RISCVCPU),
148 if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) { in check_zicbo_envcfg()
257 uint64_t menvcfg; member
725 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | in riscv_cpu_reset_hold()766 env->menvcfg = 0; in riscv_cpu_reset_hold()