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Searched refs:mcyclecfg (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c1057 *val = env->mcyclecfg; in read_mcyclecfg()
1067 env->mcyclecfg = val; in write_mcyclecfg()
1077 env->mcyclecfg = val & inh_avail_mask; in write_mcyclecfg()
1245 env->mcyclecfg; in riscv_pmu_ctr_get_fixed_counters_val()
1538 env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask); in rmw_cd_ctr_cfg()
1540 *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH; in rmw_cd_ctr_cfg()
H A Dcpu.h406 target_ulong mcyclecfg; member