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Searched refs:mcause (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dmachine.c444 VMSTATE_UINTTL(env.mcause, RISCVCPU),
H A Dcpu_helper.c2432 env->mcause = cause | ((target_ulong)async << (mxlen - 1)); in riscv_cpu_do_interrupt()
2434 env->mtval2 = env->mcause; in riscv_cpu_do_interrupt()
2435 env->mcause = RISCV_EXCP_DOUBLE_TRAP; in riscv_cpu_do_interrupt()
H A Dcpu.h310 target_ulong mcause; member
H A Dcsr.c3143 *val = env->mcause; in read_mcause()
3150 env->mcause = val; in write_mcause()
H A Dcpu.c719 env->mcause = 0; in riscv_cpu_reset_hold()