Home
last modified time | relevance | path

Searched refs:masked (Results 1 – 25 of 26) sorted by relevance

12

/qemu/hw/intc/
H A Dioapic.c50 uint8_t masked; member
65 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; in ioapic_entry_parse()
106 if (!info.masked) { in ioapic_service()
202 if (!info.masked) { in ioapic_update_kvm_routes()
H A Dspapr_xive_kvm.c197 bool masked; in kvmppc_xive_set_source_config() local
206 masked = xive_eas_is_masked(eas); in kvmppc_xive_set_source_config()
214 kvm_src |= ((uint64_t) masked << KVM_XIVE_SOURCE_MASKED_SHIFT) & in kvmppc_xive_set_source_config()
H A Dtrace-events62 xics_masked_pending(void) "set_irq_msi: masked pending"
/qemu/hw/pci/
H A Dtrace-events19 msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %d masked %d"
/qemu/host/include/generic/host/
H A Dstore-insert-al16.h.inc17 * Atomically store @val to @p masked by @msk.
/qemu/host/include/aarch64/host/
H A Dstore-insert-al16.h.inc17 * Atomically store @val to @p masked by @msk.
/qemu/qapi/
H A Dmisc-i386.json420 # @masked: port is masked
431 'masked': 'bool'} }
/qemu/hw/ppc/
H A Dpnv_psi.c224 bool masked; in pnv_psi_power8_set_irq() local
259 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; in pnv_psi_power8_set_irq()
260 if (state && !masked) { in pnv_psi_power8_set_irq()
/qemu/hw/xen/
H A Dxen_pt_msi.c160 bool masked) in msi_msix_update() argument
176 gflags |= masked ? 0 : (1u << XEN_PT_GFLAGSSHIFT_UNMASKED); in msi_msix_update()
/qemu/docs/specs/
H A Drocker.rst148 1 = masked)
291 interrupt is disabled (auto-masked*). In response to the interrupt, the driver
296 masked but the device generates an interrupt, signaling the driver that more
784 must be completely masked
791 must be completely masked
840 must be completely masked
848 must be completely masked
H A Divshmem-spec.rst120 masked by the Interrupt Mask register. The device is not capable to
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dtestcpuid.py260 desc.append("Register values have been masked:")
/qemu/target/arm/tcg/
H A Dop_helper.c1254 bool masked = (env->daif & PSTATE_A); in HELPER() local
1257 if (pending && masked) { in HELPER()
/qemu/target/ppc/
H A Dpower8-pmu-regs.c.inc75 /* Add the masked gprn bits into 'ret' */
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc289 * 2. Destination vector register group for a masked vector
339 * 2. Destination vector register group for a masked vector
424 * 1. Destination vector register group for a masked vector
458 * 3. The destination vector register group for a masked vector
486 * 4. Destination vector register group for a masked vector
513 * 5. Destination vector register group for a masked vector
635 * 3. Destination vector register group for a masked vector
745 /* masked unit stride load */
789 /* masked unit stride store */
987 * Set masked-off elements in the destination vector register to 1s.
[all …]
/qemu/linux-headers/asm-x86/
H A Dkvm.h350 __u8 masked; member
/qemu/accel/tcg/
H A Dldst_atomicity.c.inc665 * Atomically store @val to @p, masked by @msk.
685 * Atomically store @val to @p masked by @msk.
/qemu/system/
H A Dmemory_ldst.c.inc264 /* warning: addr must be aligned. The ram page is not masked as dirty
/qemu/hw/i386/kvm/
H A Dxen_evtchn.c2318 info->masked = test_bit(i, mask); in qmp_xen_event_list()
2373 if (info->masked) { in hmp_xen_event_list()
/qemu/target/sparc/
H A Dinsns.decode264 # For v7, the entire simm13 field is present, but masked to 7 bits.
/qemu/hw/nvme/
H A Dtrace-events4 pci_nvme_irq_masked(void) "IRQ is masked"
/qemu/target/i386/kvm/
H A Dkvm.c5051 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); in kvm_put_vcpu_events()
5121 if (events.nmi.masked) { in kvm_get_vcpu_events()
6354 * specific message was masked out. Skip this one. in kvm_arch_add_msi_route_post()
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc1096 /* Compare masked address with the TLB entry. */
/qemu/tcg/riscv/
H A Dtcg-target.c.inc1741 /* Compare masked address with the TLB entry. */
/qemu/tcg/ppc/
H A Dtcg-target.c.inc1090 /* Load masked 16-bit value. */

12