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Searched refs:is_secure (Results 1 – 5 of 5) sorted by relevance

/qemu/target/arm/tcg/
H A Dm_helper.c367 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() local
369 bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); in HELPER()
370 bool splimviol = env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_MASK; in HELPER()
371 uint32_t fpcar = env->v7m.fpcar[is_secure]; in HELPER()
373 bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); in HELPER()
380 if (!v7m_cpacr_pass(env, is_secure, is_priv)) { in HELPER()
381 armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_secure); in HELPER()
382 env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; in HELPER()
384 } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { in HELPER()
395 mmu_idx = arm_v7m_mmu_idx_all(env, is_secure, is_priv, negpri); in HELPER()
[all …]
H A Dhflags.c586 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in arm_get_tb_cpu_state() local
587 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { in arm_get_tb_cpu_state()
/qemu/target/arm/
H A Ddebug_helper.c267 bool is_secure = arm_is_secure(env); in bp_wp_matches() local
315 if (is_secure) { in bp_wp_matches()
320 if (!is_secure) { in bp_wp_matches()
H A Dinternals.h1248 bool is_secure, bool is_priv) in v7m_cpacr_pass() argument
1250 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { in v7m_cpacr_pass()
1614 bool is_secure, GetPhysAddrResult *result,
H A Dptw.c234 bool is_secure = arm_space_is_secure(space); in regime_translation_disabled() local
235 switch (env->v7m.mpu_ctrl[is_secure] & in regime_translation_disabled()
2327 bool is_secure, bool is_user) in pmsav7_use_background_region() argument
2340 return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; in pmsav7_use_background_region()
2774 bool is_secure, V8M_SAttributes *sattrs) in v8m_security_lookup() argument
2802 sattrs->ns = !is_secure; in v8m_security_lookup()