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Searched refs:int_status (Results 1 – 15 of 15) sorted by relevance

/qemu/hw/audio/
H A Dasc.c135 fs->int_status |= ASC_FIFO_STATUS_HALF_FULL; in asc_fifo_get()
138 fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL; in asc_fifo_get()
148 fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY; in asc_fifo_get()
267 s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL | in generate_fifo()
269 s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL | in generate_fifo()
391 fs->int_status |= ASC_FIFO_STATUS_HALF_FULL; in asc_fifo_write()
394 fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL; in asc_fifo_write()
404 fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY; in asc_fifo_write()
443 prev = (s->fifos[0].int_status & 0x3) | in asc_read()
444 (s->fifos[1].int_status & 0x3) << 2; in asc_read()
[all …]
/qemu/tests/qtest/
H A Dxlnx-can-test.c91 uint32_t int_status; in read_data() local
94 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; in read_data()
96 g_assert_cmpint(int_status, ==, ISR_RXOK); in read_data()
111 uint32_t int_status; in send_data() local
120 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; in send_data()
122 g_assert_cmpint(int_status, ==, ISR_TXOK); in send_data()
H A Dxlnx-canfd-test.c186 uint32_t int_status; in read_data() local
192 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; in read_data()
194 g_assert_cmpint(int_status, ==, ISR_RXOK); in read_data()
239 uint32_t int_status; in send_data() local
245 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; in send_data()
247 g_assert_cmpint(int_status, ==, ISR_TXOK); in send_data()
/qemu/hw/display/
H A Dpl110.c69 uint32_t int_status; member
95 VMSTATE_UINT32(int_status, PL110State),
371 if (s->int_status & s->int_mask) { in pl110_update()
383 s->int_status |= (PL110_IE_NB | PL110_IE_VC); in pl110_vblank_interrupt()
425 return s->int_status; in pl110_read()
427 return s->int_status & s->int_mask; in pl110_read()
504 s->int_status &= ~val; in pl110_write()
/qemu/hw/input/
H A Dlasips2.c55 VMSTATE_UINT8(int_status, LASIPS2State),
133 int level = s->int_status ? 1 : 0; in lasips2_update_irq()
144 s->int_status |= BIT(n); in lasips2_set_irq()
146 s->int_status &= ~BIT(n); in lasips2_set_irq()
238 if (lp->lasips2->int_status) { in lasips2_reg_read()
/qemu/hw/dma/
H A Dbcm2835_dma.c129 s->int_status |= (1 << c); in bcm2835_dma_update()
219 s->int_status &= ~(1 << c); in bcm2835_dma_write()
250 return s->int_status; in bcm2835_dma0_read()
335 VMSTATE_UINT32(int_status, BCM2835DMAState),
370 s->int_status = 0; in bcm2835_dma_reset()
H A Dpl330.c265 uint32_t int_status; member
297 VMSTATE_UINT32(int_status, PL330State),
897 ch->parent->int_status |= (1 << ev_id); in pl330_dmasev()
1355 if (s->int_status & s->inten & value & (1 << i)) { in pl330_iomem_write()
1361 s->int_status &= ~(value & s->inten); in pl330_iomem_write()
1468 return s->int_status; in pl330_iomem_read_imp()
1535 s->int_status = 0; in pl330_reset()
/qemu/hw/gpio/
H A Daspeed_gpio.c288 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); in aspeed_evaluate_irq()
629 value = set->int_status; in aspeed_gpio_read()
741 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_write_index_mode()
753 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_write_index_mode()
888 cleared = ctpop32(data & set->int_status); in aspeed_gpio_write()
893 set->int_status &= ~data; in aspeed_gpio_write()
1043 extract32(set->int_status, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1168 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_2700_write_control_reg()
1180 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_2700_write_control_reg()
1230 value = (uint64_t) set->int_status; in aspeed_gpio_2700_read()
[all …]
/qemu/hw/m68k/
H A Dnext-cube.c101 uint32_t int_status; member
212 val = s->int_status; in next_mmio_read()
246 DPRINTF("INT Status old: %x new: %x\n", s->int_status, in next_mmio_write()
248 s->int_status = val; in next_mmio_write()
527 s->int_status |= 1 << shift; in next_irq()
556 s->int_status &= ~(1 << shift); in next_irq()
672 pc->int_status |= 0x4000000; in next_scsi_csr_write()
675 pc->int_status &= ~(0x4000000); in next_scsi_csr_write()
1225 VMSTATE_UINT32(int_status, NeXTPC),
/qemu/rust/hw/timer/hpet/src/
H A Ddevice.rs537 int_status: BqlCell<u64>, field
586 self.int_status.get() & (1 << index) != 0 in is_hpet_enabled()
617 self.int_status in init_timer()
618 .set(self.int_status.get().deposit(index, 1, u64::from(level))); in init_timer()
667 let cleared = new_val & self.int_status.get(); in set_cfg_reg()
805 Global(INT_STATUS) => self.int_status.get(), in read()
1017 vmstate_of!(HPETState, int_status),
/qemu/hw/arm/
H A Dstellaris.c101 uint32_t int_status; member
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
228 return s->int_status; in ssys_read()
232 return s->int_status & s->int_mask; in ssys_read()
335 s->int_status &= ~value; in ssys_write()
343 s->int_status |= (1 << 6); in ssys_write()
355 s->int_status |= (1 << 6); in ssys_write()
453 VMSTATE_UINT32(int_status, ssys_state),
/qemu/include/hw/dma/
H A Dbcm2835_dma.h43 uint32_t int_status; member
/qemu/include/hw/input/
H A Dlasips2.h73 uint8_t int_status; member
/qemu/include/hw/audio/
H A Dasc.h40 uint8_t int_status; member
/qemu/include/hw/gpio/
H A Daspeed_gpio.h103 uint32_t int_status; member