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Searched refs:int64 (Results 1 – 24 of 24) sorted by relevance

/qemu/tests/tcg/i386/
H A Dfloat_convd.conf5 to int64: -9223372036854775808 (INVALID)
11 to int64: -9223372036854775808 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: -9223372036854775808 (INVALID)
47 to int64: -9223372036854775808 (INVALID)
53 to int64: -2 (OK)
59 to int64: -1 (OK)
[all …]
H A Dfloat_convs.ref5 to int64: -9223372036854775808 (INVALID)
11 to int64: -9223372036854775808 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
/qemu/tests/tcg/aarch64/
H A Dfloat_convs.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
H A Dfloat_convd.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: -9223372036854775808 (INVALID)
47 to int64: -9223372036854775808 (INVALID)
53 to int64: -2 (OK)
59 to int64: -1 (OK)
[all …]
/qemu/tests/tcg/ppc64le/
H A Dfloat_convs.ref5 to int64: -9223372036854775808 (INVALID)
11 to int64: -9223372036854775808 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
/qemu/tests/tcg/hexagon/
H A Dfloat_convs.ref5 to int64: -1 (INVALID)
11 to int64: -1 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
H A Dfloat_convd.ref5 to int64: -1 (INVALID)
11 to int64: -1 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: -9223372036854775808 (INVALID)
47 to int64: -9223372036854775808 (INVALID)
53 to int64: -2 (OK)
59 to int64: -1 (OK)
[all …]
/qemu/tests/tcg/arm/
H A Dfloat_convs.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: 1 (INVALID)
23 to int64: 1 (INEXACT INVALID)
29 to int64: 1 (INEXACT INVALID)
35 to int64: 1 (INEXACT INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
H A Dfloat_convd.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: 1 (INVALID)
23 to int64: 1 (INEXACT INVALID)
29 to int64: 1 (INEXACT INVALID)
35 to int64: 1 (INEXACT INVALID)
41 to int64: 1 (INEXACT INVALID)
47 to int64: 1 (INEXACT INVALID)
53 to int64: -2 (INEXACT )
59 to int64: -1 (INEXACT )
[all …]
/qemu/tests/tcg/loongarch64/
H A Dfloat_convs.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
H A Dfloat_convd.ref5 to int64: 0 (INVALID)
11 to int64: 0 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: -9223372036854775808 (INVALID)
47 to int64: -9223372036854775808 (INVALID)
53 to int64: -2 (OK)
59 to int64: -1 (OK)
[all …]
/qemu/tests/tcg/x86_64/
H A Dfloat_convs.ref5 to int64: -9223372036854775808 (INVALID)
11 to int64: -9223372036854775808 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: 0 (INEXACT )
47 to int64: 0 (INEXACT )
53 to int64: 0 (INEXACT )
59 to int64: 0 (OK)
[all …]
H A Dfloat_convd.ref5 to int64: -9223372036854775808 (INVALID)
11 to int64: -9223372036854775808 (INVALID)
17 to int64: -9223372036854775808 (INVALID)
23 to int64: -9223372036854775808 (INVALID)
29 to int64: -9223372036854775808 (INVALID)
35 to int64: -9223372036854775808 (INVALID)
41 to int64: -9223372036854775808 (INVALID)
47 to int64: -9223372036854775808 (INVALID)
53 to int64: -2 (OK)
59 to int64: -1 (OK)
[all …]
/qemu/tests/tcg/ppc64/
H A Dvsx_f2i_nan.c22 DEFINE_VSX_F2I_FUNC(float32, int64, xvcvspsxds) in DEFINE_VSX_F2I_FUNC()
26 DEFINE_VSX_F2I_FUNC(float64, int64, xvcvdpsxds) in DEFINE_VSX_F2I_FUNC()
70 DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_and, xxland) in DEFINE_VSX_BINARY_LOGICAL_OP_INSN()
80 DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_or, xxlor) in DEFINE_VSX_BINARY_LOGICAL_OP_INSN()
187 DEFINE_VSX_ALL_EQ_FUNC(int64, vcmpequd) in DEFINE_VSX_ALL_EQ_FUNC()
230 DEFINE_VSX_F2I_TEST_FUNC(float32, int64)
234 DEFINE_VSX_F2I_TEST_FUNC(float64, int64)
/qemu/disas/
H A Dnanomips.c33 typedef int64_t int64; typedef
72 static int64 sign_extend(int64 data, int msb) in sign_extend()
350 static int64 neg_copy(uint64 d) in neg_copy()
371 static int64 encode_eu_from_s_li16(uint64 d) in encode_eu_from_s_li16()
374 return d == 127 ? -1 : (int64)d; in encode_eu_from_s_li16()
550 static int64 extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction) in extract_s__se9_20_19_18_17_16_15_14_13_12_11()
552 int64 value = 0; in extract_s__se9_20_19_18_17_16_15_14_13_12_11()
559 static int64 extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction) in extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1()
561 int64 value = 0; in extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1()
626 static int64 extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction) in extract_s__se31_0_11_to_2_20_to_12_s12()
[all …]
/qemu/tests/tcg/multiarch/
H A Dfloat_convd.c79 CONVERT_DOUBLE_TO_INT( int64, PRId64) in CONVERT_DOUBLE_TO_INT()
H A Dfloat_convs.c79 CONVERT_SINGLE_TO_INT( int64, PRId64) in CONVERT_SINGLE_TO_INT()
/qemu/target/arm/tcg/
H A Dvfp_helper.c451 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
457 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
463 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
467 VFP_CONV_FLOAT_FIX_ROUND(sq, d, 64, float64, 64, int64,
/qemu/target/loongarch/tcg/
H A Dvec_helper.c2799 DO_FTINT(float64, int64, uint64_t, uint64_t) in DO_FTINT()
2803 DO_FTINT(float32, int64, uint32_t, uint64_t) in DO_FTINT()
2806 FTINT(rne_l_d, float64, int64, uint64_t, uint64_t, float_round_nearest_even) in DO_FTINT()
2808 FTINT(rp_l_d, float64, int64, uint64_t, uint64_t, float_round_up) in DO_FTINT()
2810 FTINT(rz_l_d, float64, int64, uint64_t, uint64_t, float_round_to_zero) in DO_FTINT()
2812 FTINT(rm_l_d, float64, int64, uint64_t, uint64_t, float_round_down) in DO_FTINT()
2866 FTINT(rml_l_s, float32, int64, uint32_t, uint64_t, float_round_down)
2867 FTINT(rpl_l_s, float32, int64, uint32_t, uint64_t, float_round_up)
2868 FTINT(rzl_l_s, float32, int64, uint32_t, uint64_t, float_round_to_zero)
2869 FTINT(rnel_l_s, float32, int64, uint32_t, uint64_t, float_round_nearest_even)
[all …]
/qemu/target/ppc/
H A Dfpu_helper.c569 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
2803 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), true, \
2806 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), false, \
2810 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), false, \
2906 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2946 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2948 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2950 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2972 VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
3009 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
/qemu/tests/qapi-schema/
H A Dqapi-schema-test.json164 's64': ['int64'],
/qemu/qapi/
H A Dmigration.json2040 'data': { 'id': 'int', 'dirty-rate': 'int64' } }
2117 'data': {'*dirty-rate': 'int64',
2119 'start-time': 'int64',
2120 'calc-time': 'int64',
2195 { 'command': 'calc-dirty-rate', 'data': {'calc-time': 'int64',
H A Dblock-core.json1567 '*max-chunk': 'int64', '*min-cluster-size': 'size' } }
/qemu/docs/devel/
H A Dqapi-code-gen.rst125 ``int64`` ``int64_t`` likewise