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Searched refs:immediate (Results 1 – 25 of 45) sorted by relevance

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/qemu/target/arm/tcg/
H A Dsve.decode48 # Signed 8-bit immediate, optionally shifted left by 8.
50 # Unsigned 8-bit immediate, optionally shifted left by 8.
140 # Three operand with "memory" size, aka immediate left shift
168 # Two register operands with a 6-bit signed immediate.
171 # Two register operand, one immediate operand, with predicate,
184 # Two register operand, one immediate operand, with 4-bit predicate.
197 # Predicate output, vector and immediate input,
202 # Basic Load/Store with 9-bit immediate offset
340 # SVE bitwise shift by immediate (predicated)
440 # SVE index generation (immediate start, immediate increment)
[all …]
H A Dt16.decode84 # Load/store word/byte (immediate offset)
98 # Load/store halfword (immediate offset)
120 # Add PC/SP (immediate)
133 # Shift (immediate)
149 # Add/subtract (two low registers and immediate)
157 # Add, subtract, compare, move (one low register and immediate)
178 # Adjust SP (immediate)
H A Dt32.decode166 # Data-processing (immediate)
207 # Data processing (plain binary immediate)
425 # Load/store (register, immediate, literal)
465 PLD 1111 1000 1001 ---- 1111 ------------ # (immediate T1)
470 PLD 1111 1000 0001 ---- 1111 1100 -------- # (immediate T2)
485 PLDW 1111 1000 1011 ---- 1111 ------------ # (immediate T1)
490 PLDW 1111 1000 0011 ---- 1111 1100 -------- # (immediate T2)
513 PLI 1111 1001 1001 ---- 1111 ------------ # (immediate T1)
518 PLI 1111 1001 0001 ---- 1111 1100 -------- # (immediate T2)
735 # LE and WLS immediate
H A Da32.decode111 # Data-processing (immediate)
183 # MSR (immediate) and hints
308 # Load/Store Dual, Half, Signed Byte (immediate)
344 # Load/Store word and unsigned byte (immediate)
H A Dmve.decode37 # 1imm format immediate
399 # VIDUP, VDDUP format immediate: 1 << (immh:imml)
587 # Logical immediate operations (1 reg and modified-immediate)
599 # Shifts by immediate
H A Da64.decode107 # Add/subtract (immediate)
123 # Add/subtract (immediate with tags)
131 # Logical (immediate)
146 # Move wide (immediate)
275 # These are architecturally all "MSR (immediate)"; we decode the destination
408 # Load/store register (unscaled immediate)
477 # Load/store with an unsigned 12 bit immediate, which is scaled by the
478 # element size. The function gets the sz:imm and returns the scaled immediate.
541 # LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
1572 # Advanced SIMD scalar shift by immediate
H A Dvfp.decode229 # VCVT between floating-point and fixed-point. The immediate value
H A Dneon-dp.decode365 # 1-reg-and-modified-immediate grouping:
/qemu/target/mips/tcg/
H A Docteon.decode27 # SEQI rt, rs, immediate
29 # SNEI rt, rs, immediate
/qemu/target/i386/tcg/
H A Demit.c.inc506 uint8_t b = decode->immediate;
755 gen_ternary_sse(s, decode, (uint8_t)decode->immediate >> 4, \
770 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
1030 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
1057 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
1148 if (decode->immediate == 0) {
1178 if (decode->e.op2 == X86_TYPE_I && decode->immediate == 0) {
1488 * For immediate bit number gen_bt_mask()'s output is already a constant;
2015 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63);
2016 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63);
[all …]
H A Ddecode-new.h337 target_ulong immediate; member
/qemu/target/hexagon/imported/
H A Dalu.idef43 COND_ALU(A2_paddi,"Rd32=add(Rs32,#s8)","Conditionally Add Register and immediate",fIMMEXT(siV); RdV…
66 "Add a signed immediate to a register",
71 "Add immediate to PC",
247 "This instruction carries the 26 most-significant immediate bits for the next instruction",
255 "transfer signed immediate to register",{ fIMMEXT(siV); RdV=siV;})
273 "Combine a word and an immediate into a register pair",
279 "Combine a word and an immediate into a register pair",
435 "Subtract register from immediate",{ fIMMEXT(siV); RdV=siV-RsV;})
438 "logical AND with immediate",{ fIMMEXT(siV); RdV=RsV&siV;})
441 "logical OR with immediate",{ fIMMEXT(siV); RdV=RsV|siV;})
H A Dcompare.idef104 /* Scalar compare instructions W/ immediate */
277 "Scalar MUX register immediate",
282 "Scalar MUX register immediate",
H A Dfloat.idef131 /* More immediate bits should probably be used for more precision? */
294 /* More immediate bits should probably be used for more precision? */
H A Dmpy.idef75 "32-bit Multiply by unsigned immediate",
79 "32-bit Multiply by unsigned immediate, negate result",
83 "32-bit Multiply-Add by unsigned immediate",
87 "32-bit Multiply-Subtract by unsigned immediate",
H A Dldst.idef322 /* The set of 32-bit store immediate instructions */
332 /* The set of 32-bit store immediate instructions */
H A Dshift.idef169 Q6INSN(S4_lsli,"Rd32=lsl(#s6,Rt32)",ATTRIBS(), "Shift an immediate left by register amount",
367 ATTRIBS(), "Form mask from immediate",
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc186 /* Return true if v16 is a valid 16-bit shifted immediate. */
201 /* Return true if v32 is a valid 32-bit shifted immediate. */
224 /* Return true if v32 is a valid 32-bit shifting ones immediate. */
239 /* Return true if v32 is a valid float32 immediate. */
254 /* Return true if v64 is a valid float64 immediate. */
289 /* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
401 /* Compare and branch (immediate). */
405 /* Conditional branch (immediate). */
408 /* Test and branch (immediate). */
412 /* Unconditional branch (immediate). */
[all …]
/qemu/target/avr/
H A Dinsn.decode82 # The 22-bit immediate is partially in the opcode word,
/qemu/docs/devel/
H A Dconflict-resolution.rst26 if the problem requires immediate escalation, report the issue to the QEMU
H A Dtcg-plugins.rst65 like adding or storing an immediate value. It is also possible to execute a
/qemu/target/hexagon/idef-parser/
H A DREADME.rst58 - Fill in the output function signature with the immediate integers
169 value in case of an immediate constant, and decorates the token with the
236 immediate value 1234
253 ``riV``, etc. refer to immediate arguments and will map to C integers.
400 iterate on immediate values, therefore their iteration ranges are always known
/qemu/target/microblaze/
H A Dinsns.decode44 # Officially typeb, but any immediate extension is unused.
/qemu/tcg/arm/
H A Dtcg-target.c.inc224 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
243 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */
421 /* Return true if v16 is a valid 16-bit shifted immediate. */
436 /* Return true if v32 is a valid 32-bit shifted immediate. */
459 /* Return true if v32 is a valid 32-bit shifting ones immediate. */
494 /* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
613 not wish to include an immediate shift at this point. */
1454 * isn't worth checking for an immediate operand for BIC.
1801 * shifted immediate from pc.
/qemu/target/ppc/translate/
H A Dspe-impl.c.inc80 /* SPE logic immediate */
230 /* SPE arithmetic immediate */

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