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Searched refs:i2 (Results 1 – 14 of 14) sorted by relevance

/qemu/tests/tcg/s390x/
H A Dvrep.c28 vrep(S390Vector *v1, const S390Vector *v3, const uint16_t i2, const uint8_t m4) in vrep() argument
36 , [i2] "i" (i2) in vrep()
/qemu/hw/nvram/
H A Dxlnx-efuse-crc.c77 const uint32_t i2 = (1 << 2) - 1; in xlnx_efuse_u37_crc() local
98 i = i2 & (crc ^ w); in xlnx_efuse_u37_crc()
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc44 C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32)
45 D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL)
46 C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32)
47 C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
48 D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEUQ)
49 C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64)
51 C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
57 C(0xa70a, AHI, RI_a, Z, r1, i2, new, r1_32, add, adds32)
58 C(0xa70b, AGHI, RI_a, Z, r1, i2, r1, 0, add, adds64)
79 D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_TEUQ)
[all …]
H A Dfpu_helper.c557 uint64_t HELPER(cgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) in HELPER()
560 float128 v2 = ARG128(i2); in HELPER()
606 uint64_t HELPER(cfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) in HELPER()
609 float128 v2 = ARG128(i2); in HELPER()
655 uint64_t HELPER(clgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) in HELPER()
658 float128 v2 = ARG128(i2); in HELPER()
704 uint64_t HELPER(clfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) in HELPER()
707 float128 v2 = ARG128(i2); in HELPER()
H A Dtranslate.c1467 disas_jdest(s, i2, is_imm, imm, o->in2); in op_basi()
1494 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bc()
1517 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bct32()
1524 int imm = get_field(s, i2); in op_bcth()
1556 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bct64()
1580 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bx32()
1604 disas_jdest(s, i2, is_imm, imm, o->in2); in op_bx64()
2229 TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2)); in op_diag()
3120 const uint8_t monitor_class = get_field(s, i2); in op_mc()
4311 uint64_t i2 = get_field(s, i2); in op_stnosm() local
[all …]
H A Dtranslate_vx.c.inc354 const uint16_t i2 = get_field(s, i2);
356 if (i2 == (i2 & 0xff) * 0x0101) {
362 generate_byte_mask(i2 & 0xff));
366 tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
368 tcg_gen_movi_i64(t, generate_byte_mask(i2));
378 const uint8_t i2 = get_field(s, i2) & (bits - 1);
389 for (i = i2; ; i = (i + 1) % bits) {
580 tmp = tcg_constant_i64((int16_t)get_field(s, i2));
953 const uint8_t i2 = extract32(get_field(s, m4), 2, 1);
958 read_vec_element_i64(t0, get_field(s, v2), i2, ES_64);
[all …]
/qemu/tcg/
H A Dtcg.c542 const TCGMovExtend *i2, int scratch) in tcg_out_movext2() argument
545 TCGReg src2 = i2->src; in tcg_out_movext2()
549 tcg_out_movext1(s, i2); in tcg_out_movext2()
552 if (i2->dst == src1) { in tcg_out_movext2()
554 TCGType src2_type = i2->src_type; in tcg_out_movext2()
558 src1 = i2->src; in tcg_out_movext2()
566 tcg_out_movext1_new_src(s, i2, src2); in tcg_out_movext2()
583 const TCGMovExtend *i2, const TCGMovExtend *i3, in tcg_out_movext3() argument
587 TCGReg src2 = i2->src; in tcg_out_movext3()
592 tcg_out_movext2(s, i2, i3, scratch); in tcg_out_movext3()
[all …]
H A Dtci.c127 static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) in tci_args_rrs() argument
131 *i2 = sextract32(insn, 16, 16); in tci_args_rrs()
135 uint8_t *i2, uint8_t *i3) in tci_args_rrbb() argument
139 *i2 = extract32(insn, 16, 6); in tci_args_rrbb()
/qemu/tests/decode/
H A Dsucc_named_field.decode14 i2 ........ 00000001 ........ ........ @foo alpha=2
/qemu/tcg/s390x/
H A Dtcg-target.c.inc683 static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
685 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
689 TCGReg r1, TCGReg r3, int i2)
692 tcg_out16(s, i2);
697 int i2, int m3)
700 tcg_out32(s, (i2 << 16) | (op & 0xff));
703 static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
706 tcg_out32(s, i2);
741 TCGReg v1, uint16_t i2, int m3)
745 tcg_out16(s, i2);
[all …]
/qemu/docs/devel/
H A Dtcg-ops.rst858 * - shli_vec *v0*, *v1*, *i2*
862 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e.
870 * - shri_vec *v0*, *v1*, *i2*
872 sari_vec *v0*, *v1*, *i2*
874 rotli_vec *v0*, *v1*, *i2*
/qemu/tcg/tci/
H A Dtcg-target.c.inc220 TCGReg r0, TCGReg r1, intptr_t i2)
224 tcg_debug_assert(i2 == sextract32(i2, 0, 16));
228 insn = deposit32(insn, 16, 16, i2);
/qemu/target/xtensa/
H A Dtranslate.c6132 int o0, int i0, int i1, int i2) in get_f32_o1_i3() argument
6147 if (i2 >= 0) { in get_f32_o1_i3()
6148 arg32[i2].in = tcg_temp_new_i32(); in get_f32_o1_i3()
6149 tcg_gen_extrl_i64_i32(arg32[i2].in, arg[i2].in); in get_f32_o1_i3()
6161 if (i2 >= 0) { in get_f32_o1_i3()
6162 arg32[i2].in = arg[i2].in; in get_f32_o1_i3()
6168 int o0, int i0, int i1, int i2) in put_f32_o1_i3() argument
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc68 "%i2",