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Searched refs:hstateen (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c63 if (!(env->hstateen[index] & bit)) { in smstateen_acc_ok()
526 static RISCVException hstateen(CPURISCVState *env, int csrno) in hstateen() function
560 if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { in sstateen()
3492 *val = env->hstateen[index] & env->mstateen[index]; in read_hstateen()
3503 reg = &env->hstateen[index]; in write_hstateen()
3550 *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); in read_hstateenh()
3561 reg = &env->hstateen[index]; in write_hstateenh()
3596 *val &= env->hstateen[index]; in read_sstateen()
3612 wr_mask &= env->hstateen[index]; in write_sstateen()
5900 [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
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H A Dmachine.c276 VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
H A Dcpu.h470 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; member