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Searched refs:hit (Results 1 – 19 of 19) sorted by relevance

/qemu/hw/i386/
H A Dtdvf-hob.c102 EFI_HOB_HANDOFF_INFO_TABLE *hit; in tdvf_hob_create() local
105 hit = tdvf_get_area(&hob, sizeof(*hit)); in tdvf_hob_create()
106 *hit = (EFI_HOB_HANDOFF_INFO_TABLE) { in tdvf_hob_create()
109 .HobLength = cpu_to_le16(sizeof(*hit)), in tdvf_hob_create()
129 hit->EfiEndOfHobList = tdvf_current_guest_addr(&hob); in tdvf_hob_create()
H A Dtrace-events29 vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit si…
31 …, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen) "IOTLB context hit bus 0x%"PRIx8" devf…
99 amdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb…
/qemu/target/microblaze/
H A Dmmu.c84 unsigned int i, hit = 0; in mmu_translate() local
169 hit = 1; in mmu_translate()
177 vaddr, rw, tlb_wr, tlb_ex, hit); in mmu_translate()
178 return hit; in mmu_translate()
303 int hit; in mmu_write() local
311 hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK, in mmu_write()
313 if (hit) { in mmu_write()
H A Dhelper.c91 unsigned int hit; in mb_cpu_tlb_fill() local
106 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); in mb_cpu_tlb_fill()
107 if (likely(hit)) { in mb_cpu_tlb_fill()
280 unsigned int hit; in mb_cpu_get_phys_page_attrs_debug() local
287 hit = mmu_translate(cpu, &lu, addr, 0, 0); in mb_cpu_get_phys_page_attrs_debug()
288 if (hit) { in mb_cpu_get_phys_page_attrs_debug()
/qemu/hw/arm/
H A Dtrace-events28 …, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x…
29 …, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0…
57 …, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
58 … uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
/qemu/tests/qtest/migration/
H A Dprecopy-tests.c375 int max_try_count, hit = 0; in test_auto_converge() local
434 hit = 1; in test_auto_converge()
440 g_assert_cmpint(hit, ==, 1); in test_auto_converge()
990 int hit = 0; in test_vcpu_dirty_limit() local
1040 hit = 1; in test_vcpu_dirty_limit()
1045 g_assert_cmpint(hit, ==, 1); in test_vcpu_dirty_limit()
1047 hit = 0; in test_vcpu_dirty_limit()
1062 hit = 1; in test_vcpu_dirty_limit()
1067 g_assert_cmpint(hit, ==, 1); in test_vcpu_dirty_limit()
/qemu/target/i386/tcg/system/
H A Dbpt_helper.c298 int i, hit = 0; in helper_bpt_io() local
306 hit |= 1 << i; in helper_bpt_io()
311 if (hit) { in helper_bpt_io()
312 env->dr[6] = (env->dr[6] & ~0xf) | hit; in helper_bpt_io()
/qemu/gdbstub/
H A Dtrace-events32 gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\…
/qemu/docs/system/ppc/
H A Damigang.rst59 and set ``Boot device 1`` to ``Onboard VIA IDE CDROM``. Then hit escape until
60 the main screen appears again, hit escape once more and from the exit menu that
/qemu/accel/tcg/
H A Dcpu-exec.c244 goto hit; in tb_lookup()
255 hit: in tb_lookup()
/qemu/target/arm/
H A Dptw.c2582 bool hit = false; in pmsav8_mpu_lookup() local
2613 hit = true; in pmsav8_mpu_lookup()
2615 hit = true; in pmsav8_mpu_lookup()
2618 hit = true; in pmsav8_mpu_lookup()
2681 hit = true; in pmsav8_mpu_lookup()
2685 if (!hit) { in pmsav8_mpu_lookup()
/qemu/hw/net/rocker/
H A Drocker_of_dpa.c947 void (*hit)(OfDpaFlowContext *fc, OfDpaFlow *flow); member
973 .hit = of_dpa_bridging_learn,
993 .hit = of_dpa_acl_hit,
1030 if (ops->hit) { in of_dpa_flow_ig_tbl()
1031 ops->hit(fc, flow); in of_dpa_flow_ig_tbl()
/qemu/qapi/
H A Dcxl.json246 # @reinit-threshold: REINIT threshold hit.
329 # @retry-threshold: Retry threshold hit in the Local Retry State
H A Dmachine.json734 # hit latency.
/qemu/docs/specs/
H A Dppc-spapr-xive.rst129 In some cases (old host kernels or KVM nested guests), one may hit a
/qemu/docs/system/
H A Dgdb.rst171 current instruction. This means you may hit the same breakpoint a number
/qemu/docs/devel/
H A Dsubmitting-a-patch.rst618 their tree. Occasionally, the maintainer's pull request may hit more
/qemu/docs/interop/
H A Dqcow2.rst61 hit other limits first (such as a file system's
/qemu/
H A Dqemu-options.hx555 'access\|read\|write' hit latency or 'access\|read\|write' hit