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Searched refs:henvcfg (Results 1 – 6 of 6) sorted by relevance

/qemu/target/riscv/
H A Dcpu_helper.c85 return env->henvcfg & HENVCFG_LPE; in cpu_get_fcfien()
114 return env->henvcfg & HENVCFG_SSE; in cpu_get_bcfien()
131 return (env->henvcfg & HENVCFG_DTE) != 0; in riscv_env_smode_dbltrp_enabled()
158 return get_field(env->henvcfg, HENVCFG_PMM); in riscv_pm_get_pmm()
193 return get_field(env->henvcfg, HENVCFG_PMM); in riscv_pm_get_virt_pmm()
606 get_field(env->henvcfg, HENVCFG_LPE)) { in riscv_cpu_swap_hypervisor_regs()
1314 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); in get_physical_address()
1315 adue = adue && (env->henvcfg & HENVCFG_ADUE); in get_physical_address()
2302 dte = (env->henvcfg & HENVCFG_DTE) != 0; in riscv_cpu_do_interrupt()
H A Dcsr.c605 get_field(env->henvcfg, HENVCFG_STCE))) { in sstc()
3211 return write_henvcfg(env, CSR_HENVCFG, env->henvcfg, ra); in write_menvcfg()
3239 return write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32, ra); in write_menvcfgh()
3280 (env->virt_enabled ? get_field(env->henvcfg, HENVCFG_SSE) : true)) { in write_senvcfg()
3308 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | in read_henvcfg()
3345 env->henvcfg = val & mask; in write_henvcfg()
3346 if ((env->henvcfg & HENVCFG_DTE) == 0) { in write_henvcfg()
3363 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | in read_henvcfgh()
3380 env->henvcfg = (env->henvcfg & 0xFFFFFFFF) | (valh & mask); in write_henvcfgh()
3381 if ((env->henvcfg & HENVCFG_DTE) == 0) { in write_henvcfgh()
[all …]
H A Dmachine.c298 VMSTATE_UINT64(env.henvcfg, RISCVCPU),
H A Dop_helper.c153 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg()
H A Dcpu.h472 uint64_t henvcfg; member
H A Dcpu.c728 env->henvcfg = 0; in riscv_cpu_reset_hold()