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Searched refs:hartid (Results 1 – 6 of 6) sorted by relevance

/qemu/hw/intc/
H A Driscv_aclint.c60 int hartid, in riscv_aclint_mtimer_write_timecmp() argument
70 hartid = hartid - mtimer->hartid_base; in riscv_aclint_mtimer_write_timecmp()
72 mtimer->timecmp[hartid] = value; in riscv_aclint_mtimer_write_timecmp()
73 if (mtimer->timecmp[hartid] <= rtc) { in riscv_aclint_mtimer_write_timecmp()
78 qemu_irq_raise(mtimer->timer_irqs[hartid]); in riscv_aclint_mtimer_write_timecmp()
83 qemu_irq_lower(mtimer->timer_irqs[hartid]); in riscv_aclint_mtimer_write_timecmp()
84 diff = mtimer->timecmp[hartid] - rtc; in riscv_aclint_mtimer_write_timecmp()
109 timer_mod(mtimer->timers[hartid], next); in riscv_aclint_mtimer_write_timecmp()
131 size_t hartid = mtimer->hartid_base + in riscv_aclint_mtimer_read() local
133 CPUState *cpu = cpu_by_arch_id(hartid); in riscv_aclint_mtimer_read()
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H A Dsifive_plic.c121 uint32_t hartid = plic->addr_config[addrid].hartid; in sifive_plic_update() local
127 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update()
130 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update()
299 int addrid, hartid, modes, m; in parse_hart_config() local
304 addrid = 0, hartid = 0, modes = 0; in parse_hart_config()
310 hartid++; in parse_hart_config()
325 hartid++; in parse_hart_config()
330 plic->num_harts = hartid; in parse_hart_config()
334 addrid = 0, hartid = plic->hartid_base; in parse_hart_config()
339 hartid++; in parse_hart_config()
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H A Driscv_imsic.c348 RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid)); in riscv_imsic_realize()
349 CPUState *cpu = cpu_by_arch_id(imsic->hartid); in riscv_imsic_realize()
396 DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0),
445 DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, in type_init()
449 CPUState *cpu = cpu_by_arch_id(hartid); in type_init()
463 qdev_prop_set_uint32(dev, "hartid", hartid); in type_init()
/qemu/include/hw/intc/
H A Driscv_imsic.h60 uint32_t hartid; member
65 DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
H A Dsifive_plic.h41 uint32_t hartid; member
/qemu/target/riscv/
H A Dtrace-events2 riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *de…