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/qemu/docs/specs/
H A Dvmgenid.rst11 The VM generation ID (``vmgenid``) device is an emulated device which
27 generation ID support in a virtualization platform" section of
31 - **R1a** The generation ID shall live in an 8-byte aligned buffer.
33 - **R1b** The buffer holding the generation ID shall be in guest RAM,
36 - **R1c** The buffer holding the generation ID shall be kept separate from
42 - **R1e** The generation ID shall not live in a page frame that could be
44 generation ID lives in RAM, ROM or MMIO, it shall only be mapped as
241 (QEMU) query-vm-generation-id
/qemu/docs/system/
H A Dcpu-models-mips.rst.inc11 matches the generation of the host CPUs in use. In a deployment with a
43 matches the generation of the host CPUs in use. In a deployment with a
87 matches the generation of the host CPUs in use. In a deployment with a
H A Dtarget-s390x.rst11 When using KVM as accelerator, QEMU can emulate CPUs up to the generation
H A Dcpu-models-x86.rst.inc69 matches the generation of the host CPUs in use. In a deployment with a
274 matches the generation of the host CPUs in use. In a deployment with a
/qemu/docs/devel/
H A Dmulti-thread-tcg.rst71 are only taken when code generation is required or TranslationBlocks
80 We need to protect the entire code generation cycle including any post
81 generation patching of the translated code. This also implies a shared
84 mutex for code generation. This also includes times when we need flush
89 DESIGN REQUIREMENT: Add locking around all code generation and TB
94 Code generation is serialised with mmap_lock().
105 Currently the whole system shares a single code generation buffer
167 Parallel code generation is supported. QHT is used at insertion time
301 operations if code generation is being done in a parallel context. The
H A Dblock-coroutine-wrapper.rst26 trigger the generation:
H A Dtcg-icount.rst79 point before the generation of the code which actually does
H A Dcodebase.rst60 random number generation, memory backing or cryptographic functions).
/qemu/tests/vm/
H A Dcentos-8-aarch64.ks3 # script the generation of the image.
/qemu/tests/unit/
H A Dpkix_asn1_tab.c.inc664 {"generation-qualifier", 740319234, "PrintableString"},
666 {"ub-generation-qualifier-length", 524298, "1"},
710 {"generation-qualifier", 740319234, "TeletexString"},
712 {"ub-generation-qualifier-length", 524298, "1"},
827 {"ub-generation-qualifier-length", 1342177283, "3"},
/qemu/target/hexagon/
H A DREADME129 There are also cases where we brute force the TCG code generation.
191 tree. This generation is a four step process.
258 During the TCG generation (see translate.[ch]), we use the DisasContext to
285 To track down nasty issues with Hexagon->TCG generation, we compare the
/qemu/tests/qapi-schema/
H A Dmeson.build241 # Test the document-comment document generation code by running a test schema
246 # texinfo or HTML generation, both of which have had changes. We might
257 # generation code. It also means we don't
H A Dqapi-schema-test.json72 # dummy struct to force generation of array types not otherwise mentioned
/qemu/tests/
H A Dmeson.build41 # event generation instead.
/qemu/docs/system/arm/
H A Dfby35.rst18 In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
/qemu/include/exec/
H A Dhelper-gen.h.inc4 * This one expands generation functions for tcg opcodes.
/qemu/migration/
H A Dram.c632 uint64_t generation = stat64_get(&mig_stats.dirty_sync_count); in save_xbzrle_page() local
634 if (!cache_is_cached(XBZRLE.cache, current_addr, generation)) { in save_xbzrle_page()
638 generation) == -1) { in save_xbzrle_page()
1097 uint64_t generation = stat64_get(&mig_stats.dirty_sync_count); in migration_bitmap_sync() local
1098 qapi_event_send_migration_pass(generation); in migration_bitmap_sync()
/qemu/target/arm/tcg/
H A Dsve.decode440 # SVE index generation (immediate start, immediate increment)
443 # SVE index generation (immediate start, register increment)
446 # SVE index generation (register start, immediate increment)
449 # SVE index generation (register start, register increment)
479 # SVE vector address generation
/qemu/qga/
H A Dmeson.build54 # event generation instead.
/qemu/
H A Dhmp-commands-info.hx774 .name = "vm-generation-id",
782 ``info vm-generation-id``
/qemu/include/hw/virtio/
H A Dvirtio.h131 uint32_t generation; member
/qemu/include/standard-headers/linux/
H A Dfuse.h680 uint64_t generation; /* Inode generation: nodeid:gen must member
/qemu/hw/virtio/
H A Dvirtio-mmio.c209 return vdev->generation; in virtio_mmio_read()
/qemu/docs/
H A Dimage-fuzzer.txt49 The runner activates generation of core dumps during test executions, but it
H A Digd-assign.txt50 * IGD generation is 6 to 9 (Sandy Bridge to Comet Lake)

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