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Searched refs:frm (Results 1 – 6 of 6) sorted by relevance

/qemu/target/arm/tcg/
H A Dtranslate-vfp.c338 TCGv_i64 frn, frm, dest; in trans_VSEL() local
344 frm = tcg_temp_new_i64(); in trans_VSEL()
356 vfp_load_reg64(frm, rm); in trans_VSEL()
359 tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, frn, frm); in trans_VSEL()
362 tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, frn, frm); in trans_VSEL()
367 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, frn, frm); in trans_VSEL()
370 tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, frn, frm); in trans_VSEL()
373 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, dest, frm); in trans_VSEL()
378 TCGv_i32 frn, frm, dest; in trans_VSEL() local
384 frm = tcg_temp_new_i32(); in trans_VSEL()
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/qemu/target/riscv/
H A Dtranslate.c77 int frm; member
734 if (ctx->frm == rm) { in gen_set_rm()
737 ctx->frm = rm; in gen_set_rm()
751 if (ctx->frm == rm && ctx->frm_valid) { in gen_set_rm_chkfrm()
754 ctx->frm = rm; in gen_set_rm_chkfrm()
1269 ctx->frm = -1; /* unknown rounding mode */ in riscv_tr_init_disas_context()
H A Dfpu_helper.c58 rm = env->frm; in helper_set_rounding_mode()
88 if (unlikely(env->frm >= 5)) { in helper_set_rounding_mode_chkfrm()
92 rm = env->frm; in helper_set_rounding_mode_chkfrm()
H A Dmachine.c415 VMSTATE_UINTTL(env.frm, RISCVCPU),
H A Dcpu.h221 target_ulong frm; member
H A Dcsr.c872 *val = env->frm; in read_frm()
884 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); in write_frm()
892 | (env->frm << FSR_RD_SHIFT); in read_fcsr()
904 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; in write_fcsr()