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Searched refs:fff (Results 1 – 4 of 4) sorted by relevance

/qemu/target/loongarch/
H A Dinsns.decode31 &fff fd fj fk
80 @fff .... ........ ..... fk:5 fj:5 fd:5 &fff
324 fadd_s 0000 00010000 00001 ..... ..... ..... @fff
325 fadd_d 0000 00010000 00010 ..... ..... ..... @fff
326 fsub_s 0000 00010000 00101 ..... ..... ..... @fff
327 fsub_d 0000 00010000 00110 ..... ..... ..... @fff
328 fmul_s 0000 00010000 01001 ..... ..... ..... @fff
329 fmul_d 0000 00010000 01010 ..... ..... ..... @fff
330 fdiv_s 0000 00010000 01101 ..... ..... ..... @fff
331 fdiv_d 0000 00010000 01110 ..... ..... ..... @fff
[all …]
H A Ddisas.c447 INSN(fadd_s, fff) in INSN()
448 INSN(fadd_d, fff) in INSN()
449 INSN(fsub_s, fff) in INSN()
450 INSN(fsub_d, fff) in INSN()
451 INSN(fmul_s, fff) in INSN()
452 INSN(fmul_d, fff) in INSN()
453 INSN(fdiv_s, fff) in INSN()
454 INSN(fdiv_d, fff) in INSN()
455 INSN(fmax_s, fff) in INSN()
456 INSN(fmax_d, fff) in INSN()
[all …]
/qemu/tests/tcg/aarch64/
H A Dsysregs.c136 get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff)); in main()
140 get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,0fff,00ff)); in main()
/qemu/disas/
H A Dalpha.c583 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) argument
585 #define FP(oo,fff) FP_(oo,fff), FP_MASK argument