Searched refs:dw0 (Results 1 – 8 of 8) sorted by relevance
/qemu/target/ppc/ |
H A D | mmu-hash64.h | 66 #define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58)) argument
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H A D | mmu-radix64.c | 412 if (!(pate->dw0 & PATE0_HR)) { in validate_pate() 418 if ((pate->dw0 & PATE1_R_PRTS) < 5) { in validate_pate() 452 *h_page_size = PRTBE_R_GET_RTS(pate.dw0); in ppc_radix64_partition_scoped_xlate() 454 if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB, in ppc_radix64_partition_scoped_xlate() 455 pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size, in ppc_radix64_partition_scoped_xlate()
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H A D | mmu-book3s-v3.c | 44 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); in ppc64_v3_get_pate()
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H A D | mmu-hash64.c | 525 base = pate.dw0; in ppc_hash64_hpt_base() 545 base = pate.dw0; in ppc_hash64_hpt_mask() 939 ps = PATE0_GET_PS(pate.dw0); in get_vrma_llp()
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H A D | cpu.h | 411 uint64_t dw0; member
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/qemu/hw/nvme/ |
H A D | trace-events | 87 …ion(uint16_t cid, uint16_t cqid, uint32_t dw0, uint32_t dw1, uint16_t status) "cid %"PRIu16" cqid …
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/qemu/hw/ppc/ |
H A D | spapr_nested.c | 59 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); in spapr_get_pate_nested_hv() 83 entry->dw0 = guest->parttbl[0]; in spapr_get_pate_nested_papr()
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H A D | spapr.c | 1395 entry->dw0 = spapr->patb_entry & PATE0_HR; in spapr_get_pate()
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